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The first two bits of the first or only byte of the
op code specify the length and format of the
instruction, as follows:
Bit
Positions
Instruction
Instruction
( 0-1)
Length
Format
00
One ha lfword
RR
01
Two halfwords
RX
10
Two ha lfwords
RS/S/SI
11
Three halfwords
SS
In the format illustration for each individual
instruction description, the op-code field shows the
op code as hexadecimal digits within single quotes.
The hexadecimal representation uses 0-9 for the
codes 0000-1001 and A-F for the codes
1010-1111.
The remaining fields in the format illustration
for each instruction are designated by code names,
consisting of a letter and possibly a subscript
number. The subscript number denotes the
operand to which the field applies.
Register Operands
In the RR, RX, and RS formats, the contents of the
register designated by the Rl field are called the
first operand. The register containing the first
operand is sometimes referred to as the
"first-operand location." In the RR format, the R2
field designates the register containing the second
operand, and the same register may be designated
for the first and second operand. In the RS format,
the use of the R3 field depends on the instruction.
The R field designates a general register in the
general instructions and a floating-point register in
the floating-point instructions. In the instructions
LOAD CONTROL and STORE CONTROL the R
field designates a control register.
Unless otherwise indicated in the individual
instruction description, the register operand is one
register in length (32 bits for a general register or a
control register and 64 bits for a floating-point
register), and the second operand is the same
length as the first.
Immediate Operands
In the SI format, the contents of the eight-bit
immediate-data field, the 12 field of the instruction,
are used directly as the second operand. The B
1
and D
1
fields designate the first operand, which is
one byte in length.
Storage Operands
I n the SI and SS formats, the contents of the
general register designated by the Bl field are
added to the contents of the D
1
field to form the
first-operand address. In the S, RS, and SS
formats, the contents of the general register
designated by the B2 field are added to the
contents of the D2 field to form the
second-operand address. In the RX format, the
contents of the general registers designated by the
X 2 and B2 fields are added to the contents of the
D2 field to form the second-operand address.
In the SS format, with two length fields given,
L
1
specifies the number of additional operand bytes
to the right of the byte designated by the
first-operand address. Therefore, the length in
bytes of the first operand is 1-16, corresponding to
a length code in Ll of 0-15. Similarly, L2 specifies
the number of additional operand bytes to the right
of the location designated by the second-operand
address. Results replace the first operand, and are
never stored outside the field specified by the
address and length.
If
the first operand is longer
than the second, the second operand is extended on
the left with zeros up to the length of the first
operand. This extension does not modify the
second operand in storage.
In the SS format with a single, eight-bit length
field, L specifies the number of additional operand
bytes to the right of the byte deSignated by the
first-operand address. Therefore, the length in
bytes of the first operand is 1-256, corresponding
to a length code in L of 0-255. Storage results
replace the first operand and are never stored
outside the field specified by the. address and
length. In this format, the second operand has the
same length as the first operand, except for the
following instructions: EDIT, EDIT AND MARK,
TRANSLATE, and TRANSLATE AND TEST.
RETRIEVE STATUS AND PAGE does not use the
L field, the operand lengths being fixed.
Address Generation
Execution of instructions by the CPU involves
generation of the addresses of instructions and
operands.
Sequential Instruction-Address Generation
When an instruction is fetched from the location
designated by the current PSW, the instruction
address is increased by the number of bytes in the
instruction, and the instruction is executed. The
same steps are then repeated using the new value
Chapter 5. Program Execution
5-3
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