Trace And Trigger Bus; Trace And Trigger Bus Overview - IBM A2 User Manual

Bits Function
52:54 T0_DBA
55:57 T1_DBA
58:60 T2_DBA
61:63 T3_DBA

10.12 Trace and Trigger Bus

An 88-bit debug bus is brought out of the core for use by a trace array or other debug functions implemented
at the chip level. A 12-bit bus providing trace trigger information is also made available. Together, the trace
and trigger signals provide debug data and the control signals used for starting and stopping the trace array.
Each unit has one or more debug multiplexer components, with each multiplexer requiring 16 bits of control
for selecting the debug and trigger groups from among its signals. A single 32-bit SCOM register contains two
sets of debug multiplexer control bits for controlling multiplexers in different units or within the same unit.
Tables describing each unit's debug select register and corresponding debug and trigger groups are shown in
Section C Debug and Trigger Groups on page 761.

10.12.1 Trace and Trigger Bus Overview

Each core unit shares a pass-through trace bus. As depicted in Figure 10-1, the order of trace bus data flow
from unit to unit is: AXU  PC  IU  XU  MMU. Within the XU, four debug multiplexer components are
implemented; the IU implements two. Each unit has an input for the trace bus from the previous unit, and a
pass-through multiplexer (trace bus on-ramp) to control sending the trace bus of the previous unit or its local
trace signals onto the output trace bus. The pass-through multiplexer control for the data is managed as four,
22-bit groups. The trigger bus structure is similar to the trace bus, and maintains the same unit-to-unit data
flow. Each unit can contribute up to 12 bits of trigger data onto the trigger bus. Control bits select between the
trigger bus of the previous unit or a unit's local trigger signals as two, 6-bit groups. All units default on power
up to have the pass-through state selected for the trace and trigger buses.
Version 1.3
October 23, 2012
Initial
Value
000 Additional actions that can be selected when a debug compare event
occurs for the indicated thread (sets DBCR0[EDM] status bit).
Debug Action Select:
000 No action.
000
001 Reserved (no action).
010 Stop specified thread.
000 011 Stop all threads.
100 Activate error signal (sets FIR1[52:55] for the appropriate
thread).
000 101 Activate external signal (ac_an_debug_trigger pulse).
110 Activate external signal and stop specified thread.
111 Activate external signal and stop all threads.
User's Manual
A2 Processor
Description
Debug Facilities
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