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13.3.8
MPX Interface
If the MD6 pin is set to 0 in a power-on reset, the MPX interface for normal memory is selected
for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in BCR1. The
MPX interface offers a multiplexed address/data type bus protocol, and permits easy connection to
an external memory controller chip that uses a single 32-bit multiplexed address/data bus. The
address is output to D25–D0, and the access size to D63–D61.
For details of access sizes and data alignment, see section 13.3.1, Endian/Access Size and Data
Alignment.
The address signals output at A25–A0 are undefined.
32-byte transfer performed consecutively for a total of 32 bytes according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed on the data at the 32-byte boundary. When the access size is larger than the
data bus width, as in this case, burst access is generated, with the address output once, followed by
multiple data cycles. The bus is not released during this period.
D63
D62
0
0
1
1
X
X: Don't care
SH7750 Series
RD/
D63–D0
Figure 13.51 Example of 64-Bit Data Width MPX Connection
The MPX interface timing is shown below.
When the MPX interface is used for areas 1 to 6, a bus size of 32 or 64 bits should be specified in
BCR2.
Rev. 4.0, 04/00, page 388 of 850
D61
0
1
0
1
X
CKIO
Access Size
Byte
Word
Longword
Quadword
32-byte burst
MPX device
CLK
I/O63–I/O0
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