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5.5.3
Exception Requests and BL Bit
When the BL bit in SR is 0, exceptions and interrupts are accepted.
When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's
internal registers are set to their post-reset state, the registers of the other modules retain their
contents prior to the exception, and the CPU branches to the same address as in a reset (H'A000
0000). For the operation in the event of a user break, see section 20, User Break Controller. If an
ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit has
been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or
accepted according to the setting made by software.
Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable
multiple exception state acceptance.
5.5.4
Return from Exception Handling
The RTE instruction is used to return from exception handling. When the RTE instruction is
executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns
from the exception handling routine by branching to the SPC address. If SPC and SSR were saved
to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and
issuing the RTE instruction.
Rev. 2.0, 03/99, page 91 of 396
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