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Reset
requested?
No
Execute next instruction
General
exception requested?
No
Interrupt
requested?
No
Figure 5.2 Instruction Execution and Exception Handling
5.5.2
Exception Source Acceptance
A priority ranking is provided for all exceptions for use in determining which of two or more
simultaneously generated exceptions should be accepted. Five of the general exceptions—the
general illegal instruction exception, slot illegal instruction exception, general FPU disable
exception, slot FPU disable exception, and unconditional trap exception—are detected in the
process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These
exceptions therefore all have the same priority. General exceptions are detected in the order of
instruction execution. However, exception handling is performed in the order of instruction flow
(program order). Thus, an exception for an earlier instruction is accepted before that for a later
instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3.
Yes
Is highest-
Yes
priority exception
re-exception
type?
No
Yes
SSR ← SR
SPC ← PC
SGR ← R15
EXPEVT/INTEVT ← exception code
SR.{MD,RB,BL} ← 111
PC ← (BRCR.UBDE=1 && User_Break?
DBR: (VBR + Offset))
Yes
Cancel instruction execution
result
EXPEVT ← exception code
SR. {MD, RB, BL, FD, IMASK} ← 11101111
PC ← H'A000 0000
Rev. 2.0, 03/99, page 89 of 396
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