Instruction Cache (Ic); Configuration - Hitachi SH7750 Programming Manual

4.4

Instruction Cache (IC)

4.4.1

Configuration

Figure 4.5 shows the configuration of the instruction cache.
Effective address
31 26 25
IIX
22
MMU
19
Rev. 2.0, 03/99, page 72 of 396
[12]
8
Address array
Tag address V
0
255 19 bits 1 bit
Compare
Hit signal
Figure 4.5 Configuration of Instruction Cache
13 12 11 10 9
[11:5]
Longword (LW) selection
3
Data array
LW0 LW1 LW2 LW3
32 bits 32 bits 32 bits 32 bits
5 4 3 2 1 0
LW4 LW5 LW6 LW7
32 bits 32 bits 32 bits 32 bits
Read data