Motorola DSP56367 Manuals

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Motorola DSP56367 User Manual

Motorola DSP56367 User Manual (524 pages)

24-Bit Digital Signal Processor  
Brand: Motorola | Category: Processor | Size: 6.25 MB
Table of contents
Table Of Contents3................................................................................................................................................................
Manual Conventions29................................................................................................................................................................
Section 1 Dsp56367 Overview31................................................................................................................................................................
Dsp56300 Core Description32................................................................................................................................................................
Dsp56367 Audio Processor Architecture34................................................................................................................................................................
Dsp56300 Core Functional Blocks35................................................................................................................................................................
Data Alu Registers36................................................................................................................................................................
Program Control Unit (pcu)37................................................................................................................................................................
Internal Buses38................................................................................................................................................................
Direct Memory Access (dma)39................................................................................................................................................................
Jtag Tap And Once Module40................................................................................................................................................................
Off-chip Memory Expansion41................................................................................................................................................................
Host Interface (hdi08)42................................................................................................................................................................
Triple Timer (tec)43................................................................................................................................................................
Serial Host Interface (shi)44................................................................................................................................................................
Section 2 Signal/connection Descriptions45................................................................................................................................................................
Power48................................................................................................................................................................
Clock And Pll49................................................................................................................................................................
External Memory Expansion Port (port A)50................................................................................................................................................................
Interrupt And Mode Control52................................................................................................................................................................
Parallel Host Interface (hdi08)53................................................................................................................................................................
Serial Host Interface57................................................................................................................................................................
Enhanced Serial Audio Interface59................................................................................................................................................................
Enhanced Serial Audio Interface_163................................................................................................................................................................
Spdif Transmitter Digital Audio Interface64................................................................................................................................................................
Timer65................................................................................................................................................................
Section 3 Specifications67................................................................................................................................................................
Thermal Characteristics68................................................................................................................................................................
Dc Electrical Characteristics70................................................................................................................................................................
Ac Electrical Characteristics71................................................................................................................................................................
Internal Clocks72................................................................................................................................................................
External Clock Operation73................................................................................................................................................................
Phase Lock Loop (pll) Characteristics74................................................................................................................................................................
Reset, Stop, Mode Select, And Interrupt Timing75................................................................................................................................................................
Dram Timing88................................................................................................................................................................
Arbitration Timings111................................................................................................................................................................
Parallel Host Interface (hdi08) Timing112................................................................................................................................................................
Serial Host Interface Spi Protocol Timing121................................................................................................................................................................
Programming The Serial Clock129................................................................................................................................................................
Enhanced Serial Audio Interface Timing132................................................................................................................................................................
Digital Audio Transmitter Timing138................................................................................................................................................................
Timer Timing139................................................................................................................................................................
Gpio Timing140................................................................................................................................................................
Jtag Timing141................................................................................................................................................................
Section 4 Design Considerations143................................................................................................................................................................
Electrical Design Considerations145................................................................................................................................................................
Power Consumption Considerations146................................................................................................................................................................
Pll Performance Issues147................................................................................................................................................................
Section 5 Memory Configuration149................................................................................................................................................................
Reserved Memory Spaces160................................................................................................................................................................
External Memory Support161................................................................................................................................................................
Internal I/o Memory Map162................................................................................................................................................................
Section 6 Core Configuration167................................................................................................................................................................
Operating Mode Register (omr)168................................................................................................................................................................
Address Tracing Enable (ate) - Bit 15169................................................................................................................................................................
Operating Modes171................................................................................................................................................................
Interrupt Priority Registers173................................................................................................................................................................
Dma Request Sources179................................................................................................................................................................
Pll Initialization180................................................................................................................................................................
Jtag Identification (id) Register181................................................................................................................................................................
Section 7 General Purpose Input/output185................................................................................................................................................................
Port C Signals And Registers186................................................................................................................................................................
Section 8 Host Interface (hdi08)187................................................................................................................................................................
Interface - Host Side188................................................................................................................................................................
Hdi08 Host Port Signals190................................................................................................................................................................
Hdi08 Block Diagram191................................................................................................................................................................
Hdi08 – Dsp-side Programmer's Model192................................................................................................................................................................
Host Transmit Data Register (hotx)193................................................................................................................................................................
Hcr Host Transmit Interrupt Enable (htie) Bit 1194................................................................................................................................................................
Hcr Reserved Bits 8-15196................................................................................................................................................................
Hsr Host Transmit Data Empty (htde) Bit 1197................................................................................................................................................................
Host Base Address Register (hbar)198................................................................................................................................................................
Host Port Control Register (hpcr)199................................................................................................................................................................
Hpcr Host Request Enable (hren) Bit 4200................................................................................................................................................................
Hpcr Host Address Strobe Polarity (hasp) Bit 10201................................................................................................................................................................
Hpcr Host Chip Select Polarity (hcsp) Bit 13202................................................................................................................................................................
Host Data Register (hdr)203................................................................................................................................................................
Host Interface Dsp Core Interrupts204................................................................................................................................................................
Hdi08 – External Host Programmer's Model205................................................................................................................................................................
Interface Control Register (icr)207................................................................................................................................................................
Icr Double Host Request (hdrq) Bit 2208................................................................................................................................................................
Icr Host Flag 1 (hf1) Bit 4209................................................................................................................................................................
Icr Initialize Bit (init) Bit 7210................................................................................................................................................................
Command Vector Register (cvr)211................................................................................................................................................................
Isr Receive Data Register Full (rxdf) Bit 0212................................................................................................................................................................
Isr Host Flag 3 (hf3) Bit 4213................................................................................................................................................................
Receive Byte Registers (rxh:rxm:rxl)214................................................................................................................................................................
Host Side Registers After Reset215................................................................................................................................................................
Servicing The Host Interface216................................................................................................................................................................
Servicing Interrupts217................................................................................................................................................................
Section 9 Serial Host Interface219................................................................................................................................................................
Serial Host Interface Internal Architecture220................................................................................................................................................................
Characteristics Of The Spi Bus221................................................................................................................................................................
Shi Clock Generator222................................................................................................................................................................
Shi Input/output Shift Register (iosr)—host Side225................................................................................................................................................................
Shi Host Transmit Data Register (htx)—dsp Side226................................................................................................................................................................
Shi Slave Address Register (hsar)—dsp Side227................................................................................................................................................................
Clock Phase And Polarity (cpha And Cpol)—bits 1–0228................................................................................................................................................................
Hckr Prescaler Rate Select (hrs)—bit 2229................................................................................................................................................................
Hckr Reserved Bits—bits 23–14, 11230................................................................................................................................................................
Shi Control/status Register (hcsr)—dsp Side231................................................................................................................................................................
Hcsr Fifo-enable Control (hfifo)—bit 5232................................................................................................................................................................
Hcsr Host-request Enable (hrqe[1:0])—bits 8–7233................................................................................................................................................................
Hcsr Bus-error Interrupt Enable (hbie)—bit 10234................................................................................................................................................................
Hcsr Host Transmit Underrun Error (htue)—bit 14235................................................................................................................................................................
Host Receive Fifo Not Empty (hrne)—bit 17236................................................................................................................................................................
Characteristics Of The I 2 C Bus237................................................................................................................................................................
Shi Programming Considerations240................................................................................................................................................................
Spi Master Mode241................................................................................................................................................................
Shi Operation During Dsp Stop247................................................................................................................................................................
Section 10 Enhanced Serial Audio Interface (esai)249................................................................................................................................................................
Esai Data And Control Pins251................................................................................................................................................................
Serial Transmit 3/receive 2 Data Pin (sdo3/sdi2)252................................................................................................................................................................
Serial Transmit 5/receive 0 Data Pin (sdo5/sdi0)253................................................................................................................................................................
Transmitter Serial Clock (sckt)254................................................................................................................................................................
Frame Sync For Receiver (fsr)255................................................................................................................................................................
Frame Sync For Transmitter (fst)256................................................................................................................................................................
Esai Programming Model257................................................................................................................................................................
Tccr Transmit Prescale Modulus Select (tpm7–tpm0) - Bits 0–7258................................................................................................................................................................
Tccr Transmit Prescaler Range (tpsr) - Bit 8260................................................................................................................................................................
Tccr Tx High Frequency Clock Divider (tfp3-tfp0) - Bits 14–17261................................................................................................................................................................
Tccr Transmit Clock Polarity (tckp) - Bit 18262................................................................................................................................................................
Tccr Transmit Frame Sync Signal Direction (tfsd) - Bit 22263................................................................................................................................................................
Tcr Esai Transmit 1 Enable (te1) - Bit 1264................................................................................................................................................................
Tcr Esai Transmit 3 Enable (te3) - Bit 3265................................................................................................................................................................
Tcr Esai Transmit 5 Enable (te5) - Bit 5266................................................................................................................................................................
Tcr Transmit Frame Sync Relative Timing (tfsr) - Bit 16272................................................................................................................................................................
Tcr Transmit Exception Interrupt Enable (teie) - Bit 20273................................................................................................................................................................
Esai Receive Clock Control Register (rccr)274................................................................................................................................................................
Rccr Receiver Frame Sync Polarity (rfsp) - Bit 19275................................................................................................................................................................
Rccr Receiver High Frequency Clock Polarity (rhckp) - Bit 20276................................................................................................................................................................
Rccr Receiver High Frequency Clock Direction (rhckd) - Bit277................................................................................................................................................................
Rcr Esai Receiver 0 Enable (re0) - Bit 0278................................................................................................................................................................
Rcr Esai Receiver 2 Enable (re2) - Bit 2279................................................................................................................................................................
Rcr Receiver Frame Sync Length (rfsl) - Bit 15281................................................................................................................................................................
Rcr Receive Exception Interrupt Enable (reie) - Bit 20282................................................................................................................................................................
Esai Common Control Register (saicr)283................................................................................................................................................................
Saicr Reserved Bits - Bits 3-5, 9-23284................................................................................................................................................................
Esai Status Register (saisr)286................................................................................................................................................................
Saisr Reserved Bits - Bits 3-5, 11-12, 18-23287................................................................................................................................................................
Saisr Transmit Frame Sync Flag (tfs) - Bit 13288................................................................................................................................................................
Saisr Transmit Odd-data Register Empty (tode) - Bit 17289................................................................................................................................................................
Esai Receive Shift Registers292................................................................................................................................................................
Esai Time Slot Register (tsr)293................................................................................................................................................................
Receive Slot Mask Registers (rsma, Rsmb)294................................................................................................................................................................
Esai Interrupt Requests297................................................................................................................................................................
Operating Modes – Normal, Network, And On-demand298................................................................................................................................................................
Synchronous/asynchronous Operating Modes299................................................................................................................................................................
Shift Direction Selection300................................................................................................................................................................
Gpio - Pins And Registers301................................................................................................................................................................
Port C Direction Register (prrc)302................................................................................................................................................................
Port C Data Register (pdrc)303................................................................................................................................................................
Esai Initialization Examples304................................................................................................................................................................
Initializing Just The Esai Receiver Section305................................................................................................................................................................
Section 11 Enhanced Serial Audio Interface 1 (esai_1)307................................................................................................................................................................
Esai_1 Data And Control Pins309................................................................................................................................................................
Serial Transmit 4/receive 1 Data Pin (sdo4_1/sdi1_1)310................................................................................................................................................................
Frame Sync For Receiver (fsr_1)311................................................................................................................................................................
Esai_1 Multiplex Control Register (emuxr)312................................................................................................................................................................
Tccr_1 Tx High Freq. Clock Divider (tfp3-tfp0) - Bits 14–17313................................................................................................................................................................
Esai_1 Transmit Control Register (tcr_1)316................................................................................................................................................................
Rccr_1 Rx High Freq. Clock Divider (rfp3-rfp0) - Bits 14–17317................................................................................................................................................................
Esai_1 Common Control Register (saicr_1)318................................................................................................................................................................
Esai_1 Receive Shift Registers319................................................................................................................................................................
Esai_1 Time Slot Register (tsr_1)320................................................................................................................................................................
Receive Slot Mask Registers (rsma_1, Rsmb_1)321................................................................................................................................................................
Port E Direction Register (prre)323................................................................................................................................................................
Port E Data Register (pdre)324................................................................................................................................................................
Section 12 Digital Audio Transmitter325................................................................................................................................................................
Dax Signals326................................................................................................................................................................
Dax Functional Overview327................................................................................................................................................................
Dax Programming Model328................................................................................................................................................................
Dax Internal Architecture329................................................................................................................................................................
Dax Audio Data Buffers (xadbufa / Xadbufb)330................................................................................................................................................................
Dax Channel A Channel Status (xca)—bit 12331................................................................................................................................................................
Audio Data Register Empty Interrupt Enable (xdie)—bit 0332................................................................................................................................................................
Dax Status Register (xstr)333................................................................................................................................................................
Xstr Reserved Bits—bits 3–23334................................................................................................................................................................
Dax Clock Multiplexer335................................................................................................................................................................
Dax State Machine336................................................................................................................................................................
Audio Data Register Empty Interrupt Handling337................................................................................................................................................................
Dax Operation During Stop339................................................................................................................................................................
Port D Control Register (pcrd)340................................................................................................................................................................
Port D Data Register (pdrd)341................................................................................................................................................................
Section 13 Timer/ Event Counter343................................................................................................................................................................
Individual Timer Block Diagram344................................................................................................................................................................
Timer/event Counter Programming Model345................................................................................................................................................................
Prescaler Counter347................................................................................................................................................................
Tplr Reserved Bit 23348................................................................................................................................................................
Timer Control/status Register (tcsr)349................................................................................................................................................................
Tcsr Inverter (inv) Bit 8351................................................................................................................................................................
Tcsr Timer Reload Mode (trm) Bit 9352................................................................................................................................................................
Tcsr Data Input (di) Bit 12353................................................................................................................................................................
Tcsr Timer Compare Flag (tcf) Bit 21354................................................................................................................................................................
Timer Compare Register (tcpr)355................................................................................................................................................................
Timer Modes356................................................................................................................................................................
Timer Pulse (mode 1)357................................................................................................................................................................
Timer Toggle (mode 2)358................................................................................................................................................................
Timer Event Counter (mode 3)359................................................................................................................................................................
Measurement Accuracy360................................................................................................................................................................
Measurement Input Period (mode 5)361................................................................................................................................................................
Measurement Capture (mode 6)362................................................................................................................................................................
Pulse Width Modulation (pwm, Mode 7)363................................................................................................................................................................
Watchdog Modes364................................................................................................................................................................
Watchdog Toggle (mode 10)365................................................................................................................................................................
Reserved Modes366................................................................................................................................................................
Section 14 Packaging367................................................................................................................................................................
Lqfp Package Mechanical Drawing373................................................................................................................................................................
Ordering Drawings374................................................................................................................................................................
A.1 Dsp56367 Bootstrap Program375................................................................................................................................................................
D.1 Introduction433................................................................................................................................................................
D.2 Internal I/o Memory Map434................................................................................................................................................................
D.3 Interrupt Vector Addresses439................................................................................................................................................................
D.4 Interrupt Source Priorities (within An Ipl)442................................................................................................................................................................
D.5 Host Interface—quick Reference444................................................................................................................................................................
D.6 Programming Sheets447................................................................................................................................................................
Index517................................................................................................................................................................

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