Ssi Transmit Shift Register - Motorola DSP56156 Manual

8.7

SSI TRANSMIT SHIFT REGISTER

This is a 16-bit shift register that contains the data being transmitted. Data is shifted out
to the serial transmit data STD pin by the selected (internal/external) bit clock when the
associated frame sync I/O is asserted. The number of bits shifted out before the shift reg-
ister is considered empty and may be written to again can be 8, 12, or 16 bits as deter-
mined by the Word Length control bits in the SSI Control Register A (WL1-WL0).
The data to be transmitted occupies the most significant portion of the shift register. The
unused portion of the register is ignored. Data is shifted out of this register with the most
significant bit (MSB) first when the SHFD bit of the control register B is cleared. If the
SHFD bit is set, the LSB is output first. The Transmit Shift Register cannot be directly ac-
cessed by the programmer.
15
HIGH BYTE
15
HIGH BYTE
15
HIGH BYTE
15
HIGH BYTE
8 - 10 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)

SSI TRANSMIT SHIFT REGISTER

SSIx DATA REGISTERS
8 7
LOW BYTE
8 7
LOW BYTE
8 7
LOW BYTE
8 7
LOW BYTE
Figure 8-8 SSIx Programming Model
0
SERIAL RECEIVE
SHIFT REGISTER
(Cannot be accessed
directly)
0 READ-ONLY
SERIAL RECEIVE
REGISTER
(SSI0 Address X:$FFF1
SSI1 Address X:$FFF9)
0
SERIAL TRANSMIT
SHIFT REGISTER
(Cannot be accessed
directly)
WRITE-ONLY
0
SERIAL TRANSMIT
REGISTER
(SSI0 Address X:$FFF1
SSI1 Address X:$FFF9)
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