Program Control Unit (Pcu) - Motorola DSP56309 User Manual

DSP56309 Overview
DSP56300 Core Functional Blocks
specifies the type of arithmetic to be used in the address register update calculation. The
modifier value is decoded in the Address ALU.
1.6.3

Program Control Unit (PCU)

The PCU performs instruction prefetch, instruction decoding, hardware DO loop
control, and exception processing. The PCU implements a seven-stage pipeline and
controls the different processing states of the DSP56300 core. The PCU consists of three
hardware blocks:
¥ Program decode controller (PDC)
¥ Program address generator (PAG)
¥ Program interrupt controller
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates
all signals necessary for pipeline control. The PAG contains all the hardware needed for
program address generation, system stack, and loop control. The PIC arbitrates among
all interrupt requests (internal interrupts, as well as the five external requests IRQA,
IRQB, IRQC, IRQD, and NMI) and generates the appropriate interrupt vector address.
PCU features include the following:
¥ Position Independent Code (PIC) support
¥ Addressing modes optimized for DSP applications (including immediate offsets)
¥ On-chip instruction cache controller
¥ On-chip memory-expandable hardware stack
¥ Nested hardware DO loops
¥ Fast auto-return interrupts
The PCU implements its functions using the following registers:
¥ PCÑprogram counter register
¥ SRÑstatus register
¥ LAÑloop address register
¥ LCÑloop counter register
¥ VBAÑvector base address register
¥ SZÑsize register
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