Once Command Register; Once Register Addressing - Motorola DSP56000 Manual

24-bit digital signal processor

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OnCE CONTROLLER AND SERIAL INTERFACE

The Register Select bits define which register is source (destination) for the read (write)

operation. Table 10-2 indicates the OnCE register addresses.

Figure 10-4 OnCE Command Register

Table 10-2 OnCE Register Addressing

OnCE Status and Control Register (OSCR)

Memory Breakpoint Counter (OMBC)

Trace Counter (OTC)

Memory Upper Limit Register (OMULR)

Memory Lower Limit Register (OMLLR)

GDB Register (OGDBR)

PDB Register (OPDBR)

PAB Register for Fetch (OPABFR)

PIL Register (OPILR)

Clear Memory Breakpoint Counter (OMBC)

Clear Trace Counter (OTC)

Program Address Bus FIFO and Increment Counter

PAB Register for Decode (OPABDR)

No Register Selected

ON-CHIP EMULATION (OnCE)

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