Features; Dsp56300 Core - Motorola DSP56303 User Manual

Features

1.3 Features
The Motorola DSP56303, a member of the DSP56300 core family of programmable DSPs,
supports wireless infrastructure applications with general filtering operations. Like the other
family members, the DSP56303 uses a high-performance, single-clock-cycle- per-instruction
engine (code compatible with Motorola's popular DSP56000 core family), a barrel shifter,
24-bit addressing, instruction cache, and DMA controller. The DSP56303 offers 100 million
instructions per second (MIPS) performance using an internal 100 MHz clock with 3.3 V core
and input/output (I/O) power.
All DSP56300 core family members contain the DSP56300 core and additional modules. The
modules are chosen from a library of standard predesigned elements, such as memories and
peripherals. New modules can be added to the library to meet customer specifications. A
standard interface between the DSP56300 core and the on-chip memory and peripherals
supports a wide variety of memory and peripheral configurations. In particular, the DSP56303
includes a JTAG port integrated with the Motorola OnCE™ module.
The DSP56303 is intended for use in telecommunication applications, such as multi-line
voice/data/fax processing, video conferencing, audio applications, control, and general digital
signal processing
1.4

DSP56300 Core

Core features are fully described in the DSP56300 Family Manual. This manual, in contrast,
documents pinout, memory, and peripheral features. Core features are as follows:
100 million instructions per second (MIPS) with a 100 MHz clock at 3.0–3.6 V
Object code compatible with the DSP56000 core
Highly parallel instruction set
Data Arithmetic Logic Unit (Data ALU)
— Fully pipelined 24 x 24-bit parallel Multiplier-Accumulator (MAC)
— 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
— Conditional ALU instructions
— 24-bit or 16-bit arithmetic support under software control
Program Control Unit (PCU)
— Position Independent Code (PIC) support
— Addressing modes optimized for DSP applications (including immediate offsets)
— On-chip instruction cache controller
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