Double Precision Multiply Mode; Section 3.4 Double Precision Multiply Mode; Full Double Precision Multiply Algorithm - Motorola DSP56000 Manual

3.4

DOUBLE PRECISION MULTIPLY MODE

The Data ALU double precision multiply operation multiplies two 48-bit operands with a
96-bit result. The processor enters the dedicated Double Precision Multiply Mode when
the user sets bit 14 (DM) of the Status Register (bit 6 of the MR register). The mode is
disabled by clearing the DM bit. For information on the DM bit, see Section 5.4.2.13 -
Double Precision Multiply Mode (Bit 14).
While in the Double Precision Multiply Mode, only the double precision multiply algorithms
shown in Figure 3-11, Figure 3-12, and Figure 3-13 may be executed by the Data ALU;
any other Data ALU operation will give indeterminate results.
Figure 3-11 shows the full double precision multiply algorithm. To allow for pipeline
delay, the ANDI instruction should not be immediately followed by a Data ALU instruc-
tion. For example, the ORI instruction sets the DM mode bit, but, due to the instruction
execution pipeline, the Data ALU enters the Double Precision Multiply mode only after
R1
R0
DP3_DP2_DP1_DP0 = MSP1_LSP1 x MSP2_LSP2
ori #$40,mr
move
mpy y0,x0,a
mac x1,y0,a
mac x0,y1,a
mac y1,x1,a
move a,l:(r0)+
andi #$bf,mr
non-Data ALU operation
Figure 3-11 Full Double Precision Multiply Algorithm
3 - 16
DOUBLE PRECISION MULTIPLY MODE
CAUTION:
X:
MSP1
LSP1
DP3
DP1
x:(r1)+,x0
x:(r1)+,x1
a0,x:(r0)+
DATA ARITHMETIC LOGIC UNIT
Y:
MSP2
LSP2
DP2
DP0
;enter mode
y:(r5)+,y0 ;load operands
y:(r5)+,y1 ;LSP*LSP
a0,y:(r0) ;shifted(a)+
; MSP*LSP
;a+LSP*MSP
;shifted(a)+
; MSP*MSP
;exit mode
;pipeline delay
R5
R0
a
a
a
a
MOTOROLA