Tcs Transmitter Relative Timing (Trel)-Bit 9; Tcs Transmitter Data Word Expansion (Tdwe)-Bit 10; Figure 6-12 Transmitter Clock Polarity (Tckp) Programming; Figure 6-13 Transmitter Relative Timing (Trel) Programming - Motorola DSP56012 User Manual

Serial Audio Interface
Serial Audio Interface Programming Model
SCKT
SDO
WST

Figure 6-12 Transmitter Clock Polarity (TCKP) Programming

6.3.4.9 TCS Transmitter Relative Timing (TREL)—Bit 9
The read/write Transmitter Relative timing (TREL) control bit selects the relative
timing of the WST signal in reference to the serial data output lines (SDOx). When
TREL is cleared, the transition of WST, indicating the start of a data word, occurs
together with the first bit of that data word. When TREL is set, the transition of WST
occurs one serial clock cycle earlier (together with the last bit of the previous data
word), as required by the I
hardware reset and software reset.
TREL = 0
WST
MSB
SDO
TREL = 1
WST
LSB MSB
SDO

Figure 6-13 Transmitter Relative Timing (TREL) Programming

6.3.4.10 TCS Transmitter Data Word Expansion (TDWE)—Bit 10
The read/write Transmitter Data Word Expansion (TDWE) control bit selects the
method used to expand a 24-bit data word to 32 bits during transmission. When
TDWE is cleared, after transmitting the 24-bit data word from the transmit data
6-20
TCKP = 0
2
S format (see Figure 6-13).The TREL bit is cleared during
Left
LSB
Left
DSP56012 User's Manual
SCKT
SDO
WST
Right
MSB
Right
LSB MSB
TCKP = 1
AA0438k
LSB MSB
LSB MSB
AA0439
MOTOROLA