Icr Transmit Request Enable (Treq) Bit 1; Icr Reserved Bit - Bit 2; Icr Host Flag 0 (Hf0) Bit 3 - Motorola DSP56156 Manual

In DMA modes, RREQ must be set or cleared by software to select the direction of DMA
transfers. Setting RREQ sets the direction of the DMA transfer to be from DSP to HOST,
and enables the HREQ pin to request these data transfers. RREQ is cleared by DSP re-
set.

5.10.2 ICR Transmit Request Enable (TREQ) Bit 1

The Transmit Request enable (TREQ) bit is used to control the HREQ pin for host transmit
data transfers. In the Interrupt Mode (DMA off), TREQ is used to enable interrupt requests
via the external Host Request HREQ pin when the Transmit Data Register Empty (TXDE)
status bit in the Interrupt Status register (ISR) is set. When TREQ is cleared, TXDE inter-
rupts are disabled. When TREQ is set, the external Host Request HREQ pin will be as-
serted if TXDE is set.
In DMA modes, TREQ must be set or cleared by software to select the direction of DMA
transfers. Setting TREQ sets the direction of the DMA transfer to be from HOST to DSP,
and enables the HREQ pin to request these data transfers.
Table 5-2 and Table 5-3 summarize the effect of RREQ and TREQ on the HREQ pin.
TREQ is cleared by DSP reset.
5.10.3 ICR Reserved bit – Bit 2
This bit is reserved and unused. It reads as a logic zero. Reserved bits should be written
as zero for future compatibility.
Table 5-2 HREQ Pin Definition - Interrupt Mode
TREQ RREQ
TREQ
0
0
1
1

5.10.4 ICR Host Flag 0 (HF0) Bit 3

The Host Flag 0 (HF0) bit is used as a general purpose flag for host processor to DSP
communication. HF0 may be set or cleared by the host processor and cannot be changed
by the DSP. Changing HF0 also changes the Host Flag bit 0 (HF0) of the Host Status reg-
ister HSR on the DSP side of the HI. HF0 is cleared by DSP reset.
MOTOROLA
INTERRUPT CONTROL REGISTER (ICR)
HREQ Pin
0 0 No Interrupts (Polling)
0 1 RXDF Request (Interrupt)
1 0 TXDE Request (Interrupt)
1 1 RXDF and TXDE Request (Interrupt)
Table 5-3 HREQ Pin Definition - DMA Mode
RREQ HREQ Pin
0 DMA Transfers Disabled
1 DSP→ HOST Request (RX)
0 HOST→ DSP Request (TX)
1 Undefined (Illegal)
HOST INTERFACE 5 - 13