Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 928

23.9.17 MC—Message Signaled Interrupt Message Control
Register (KT—D22:F3)
Address Offset: D2–D3h
Default Value:
Bit
15:8
7
6:4
3:1
0
23.9.18 MA—Message Signaled Interrupt Message Address
Register (KT—D22:F3)
Address Offset: D4–D7h
Default Value:
This register specifies the DWORD aligned address programmed by system software for
sending MSI.
Bit
31:2
1:0
23.9.19 MAU—Message Signaled Interrupt Message Upper
Address Register (KT—D22:F3)
Address Offset: D8–DBh
Default Value:
Bit
31:4
3:0
928
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
0080h
Reserved
64 Bit Address Capable (C64)— RO. Capable of generating 64-bit and 32-bit
messages.
Multiple Message Enable (MME)— R/W.These bits are R/W for software
compatibility, but only one message is ever sent by the PT function.
Multiple Message Capable (MMC)— RO. Only one message is required.
MSI Enable (MSIE)— R/W. If set, MSI is enabled and traditional interrupt pins are
not used to generate interrupts.
00000000h
Address (ADDR)— R/W. Lower 32 bits of the system specified message address,
always DWord aligned.
Reserved
00000000h
Reserved
Address (ADDR)— R/W. Upper 4 bits of the system specified message address.
Attribute: RO, R/W
Size: 16 bits
Description
Attribute: RO, R/W
Size: 32 bits
Description
Attribute: RO, R/W
Size: 32 bits
Description
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