Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 847

Thermal Sensor Registers (D31:F6)
22.1.4 STS—Status
Address Offset: 06h
Default Value:
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
22.1.5 RID—Revision Identification
Address Offset: 08h
Default Value:
Bit
7:0
22.1.6 PI— Programming Interface
Address Offset: 09h
Default Value:
Bit
7:0
Datasheet
07h
–
0010h
Detected Parity Error (DPE) — R/WC. This bit is set whenever a parity error is seen
on the internal interface for this function, regardless of the setting of bit 6 in the
command register. Software clears this bit by writing a 1 to this bit location.
SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0.
Received Master Abort (RMA) — RO. Not implemented. Hardwired to 0.
Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0.
Signaled Target-Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEVT) — RO. Does not apply. Hardwired to 0.
Master Data Parity Error (MDPE) — RO. Not implemented. Hardwired to 0.
Fast Back to Back Capable (FBC) — RO. Does not apply. Hardwired to 0.
Reserved
66 MHz Capable (C66) — RO. Does not apply. Hardwired to 0.
Capabilities List Exists (CLIST) — RO. Indicates that the controller contains a
capabilities pointer list. The first item is pointed to by looking at configuration offset
34h.
Interrupt Status (IS) — RO. Reflects the state of the INTx# signal at the input of the
enable/disable circuit. This bit is a 1 when the INTx# is asserted. This bit is a 0 after
the interrupt is cleared (independent of the state of the Interrupt Disable bit in the
command register).
Reserved
00h
Revision ID (RID) — RO. Indicates the device specific revision identifier.
00h
Programming Interface (PI) — RO. The PCH Thermal logic has no standard
programming interface.
Attribute: R/WC, RO
Size: 16 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
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