System Power Planes; Smi#/Sci Generation; System Power Plane - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

Functional Description
5.13.3

System Power Planes

The system has several independent power planes, as described in
that when a particular power plane is shut off, it should go to a 0 V level.
s
Table 5-26. System Power Plane
Plane
Processor
Main
Memory
Intel ME
LAN
Deep S4/
S5 Well
DEVICE[n]
5.13.4

SMI#/SCI Generation

Upon any enabled SMI event taking place while the End of SMI (EOS) bit is set, the PCH
will clear the EOS bit and assert SMI to the processor, which will cause it to enter SMM
space. SMI assertion is performed using a Virtual Legacy Wire (VLW) message. Prior
system generations (those based upon legacy processors) used an actual SMI# pin.
Once the SMI VLW has been delivered, the PCH takes no action on behalf of active SMI
events until Host software sets the End of SMI (EOS) bit. At that point, if any SMI
events are still active, the PCH will send another SMI VLW message.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
Datasheet
Controlled By
The SLP_S3# signal can be used to cut the power to the
SLP_S3# signal
processor completely.
When SLP_S3# goes active, power can be shut off to any circuit
not required to wake the system from the S3 state. Since the S3
state requires that the memory context be preserved, power
must be retained to the main memory.
SLP_S3# signal
The processor, devices on the PCI bus, LPC I/F, and graphics will
typically be shut off when the Main power plane is off, although
there may be small subsections powered.
When SLP_S4# goes active, power can be shut off to any circuit
not required to wake the system from the S4. Since the memory
context does not need to be preserved in the S4 state, the power
SLP_S4# signal to the memory can also be shut down.
SLP_S5# signal When SLP_S5# goes active, power can be shut off to any circuit
not required to wake the system from the S5 state. Since the
memory context does not need to be preserved in the S5 state,
the power to the memory can also be shut.
This signal is asserted when the manageability platform goes to
MOff. Depending on the platform, this pin may be used to control
SLP_A#
the Intel Management Engine power planes, LAN subsystem
power, and the SPI flash power.
This signal is asserted in Sx/Moff when both host and Intel ME
SLP_LAN# WOL are not supported. This signal can be use to control power
to the Intel GbE PHY.
This signal that the Sus rails externally can be shut off for
SLP_SUS#
enhanced power saving.
Individual subsystems may have their own power plane. For
Implementation
example, GPIO signals may be used to control the power to disk
Specific
drives, audio amplifiers, or the display screen.
Table 5-26. Note
Description
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