Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 705

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Integrated Intel High Definition Audio Controller Registers
17.1.1.49 L1DESC—Link 1 Description Register
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(Intel
Address Offset: 140h–143h
Default Value:
Bit
Target Port Number — RO. The Intel
31:24
PCH's Port 0.
Target Component ID — RO. This field returns the value of the ESD.CID field of the
23:16
chip configuration section. ESD.CID is programmed by BIOS.
15:2 Reserved.
1 Link Type — RO. Hardwired to 0 indicating Type 0.
0 Link Valid — RO. Hardwired to 1.
17.1.1.50 L1ADDL—Link 1 Lower Address Register
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(Intel
Address Offset: 148h–14Bh
Default Value:
Bit
Link 1 Lower Address — RO. Hardwired to match the RCBA register value in the PCI-
31:14
LPC bridge (D31:F0:F0h).
13:0 Reserved.
17.1.1.51 L1ADDU—Link 1 Upper Address Register
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(Intel
Address Offset: 14Ch–14Fh
Default Value:
Bit
31:0 Link 1 Upper Address — RO. Hardwired to 00000000h.
Datasheet
High Definition Audio Controller—D27:F0)
00000001h
High Definition Audio Controller—D27:F0)
See Register Description
High Definition Audio Controller—D27:F0)
00000000h
Attribute: RO
Size: 32 bits
Description
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High Definition Audio controller targets the
Attribute: RO
Size: 32 bits
Description
Attribute: RO
Size: 32 bits
Description
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