Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 760

19.1.3 PCICMD—PCI Command Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 04h–05h
Default Value:
Bit
15:11 Reserved
Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled Hot-
Plug and power management events. This bit has no effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or
10 1 = Internal INTx# messages will not be generated.
This bit does not affect interrupt forwarding from devices connected to the root port.
Assert_INTx and Deassert_INTx messages will still be forwarded to the internal
interrupt controllers if this bit is set.
9 Fast Back to Back Enable (FBE) — Reserved per the PCI Express* Base Specification.
SERR# Enable (SEE) — R/W.
8
0 = Disable.
1 = Enables the root port to generate an SERR# message when PSTS.SSE is set.
7 Wait Cycle Control (WCC) — Reserved per the PCI Express Base Specification.
Parity Error Response (PER) — R/W.
0 = Disable.
6
1 = Indicates that the device is capable of reporting parity errors as a master on the
5 VGA Palette Snoop (VPS) — Reserved per the PCI Express* Base Specification.
Postable Memory Write Enable (PMWE) — Reserved per the PCI Express* Base
4
Specification.
3 Special Cycle Enable (SCE) — Reserved per the PCI Express* Base Specification.
Bus Master Enable (BME) — R/W.
0 = Disable. Memory and I/O requests received at a Root Port must be handled as
1 = Enable. Allows the root port to forward Memory and I/O Read/Write cycles onto the
2
NOTE: This bit does not affect forwarding of completions in either upstream or
Memory Space Enable (MSE) — R/W.
0 = Disable. Memory cycles within the range specified by the memory base and limit
1
1 = Enable. Allows memory cycles within the range specified by the memory base and
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are
0
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit
760
0000h
power management and MSI is not enabled.
backbone.
Unsupported Requests.
backbone from a PCI Express* device.
downstream direction nor controls forwarding of requests other than memory or
I/O
registers are master aborted on the backbone.
limit registers can be forwarded to the PCI Express device.
master aborted on the backbone.
registers can be forwarded to the PCI Express device.
PCI Express* Configuration Registers
Attribute: R/W, RO
Size: 16 bits
Description
Datasheet