Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 533

LPC Interface Bridge Registers (D31:F0)
13.8.3.12 DEVACT_STS — Device Activity Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
Each bit indicates if an access has occurred to the corresponding device's trap range, or
for bits 6:9 if the corresponding PCI interrupt is active. This register is used in
conjunction with the Periodic SMI# timer to detect any system activity for legacy power
management. The periodic SMI# timer indicates if it is the right time to read the
DEVACT_STS register (PMBASE + 44h).
Note: Software clears bits that are set in this register by writing a 1 to the bit position.
Bit
15:13
12
11:10
9
8
7
6
5:0
13.8.3.13 PM2_CNT—Power Management 2 Control
I/O Address:
Default Value:
Lockable:
Power Well:
Bit
Reserved
7:1
Arbiter Disable (ARB_DIS) — R/W This bit is a scratchpad bit for legacy software
0
compatibility.
Datasheet
PMBASE +44h
0000h
No
Core
Reserved
KBC_ACT_STS — R/WC. KBC (60/64h).
0 = Indicates that there has been no access to this device I/O range.
1 = This device I/O range has been accessed. Clear this bit by writing a 1 to the bit
location.
Reserved
PIRQDH_ACT_STS — R/WC. PIRQ[D or H].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQCG_ACT_STS — R/WC. PIRQ[C or G].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQBF_ACT_STS — R/WC. PIRQ[B or F].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQAE_ACT_STS — R/WC. PIRQ[A or E].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
Reserved
PMBASE + 50h
00h
No
Core
Attribute: R/WC
Size: 16-bit
Usage: Legacy Only
Description
Attribute: R/W
Size: 8-bit
Usage: ACPI
Description
533