Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 873

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.1.14 ME_UMA—Management Engine UMA Register
(MEI—D22:F0)
Address Offset: 44h–47h
Default Value:
Bit
31
30:7
16
15:6
5:0
23.1.15 GMES—General ME Status
(MEI—D22:F0)
Address Offset: 48h–4Bh
Default Value:
Bit
31:0
23.1.16 H_GS—Host General Status
(MEI—D22:F0)
Address Offset: 4Ch–4Fh
Default Value:
Bit
31:0
Datasheet
80000000h
Reserved — RO. Hardwired to 1. Can be used by host software to discover that this
register is valid.
Reserved
ME UMA Size Valid—RO. This bit indicates that FW has written to the MUSZ field.
Reserved
ME UMA Size (MUSZ)—RO. This field reflect ME Firmware's desired size of MEUMA
memory region. This field is set by ME firmware prior to core power bring up allowing
BIOS to initialize memory.
000000b = 0 MB, No memory allocated to MEUMA
000001b = 1 MB
000010b = 2 MB
000100b = 4 MB
001000b = 8 MB
010000b = 16 MB
100000b = 32 MB
00000000h
General ME Status (ME_GS)— RO. This field is populated by ME.
00000000h
Host General Status(H_GS)— RO. General Status of Host, this field is not used by
Hardware
Attribute: RO
Size: 32 bits
Description
Attribute: RO
Size: 32 bits
Description
Attribute: RO
Size: 32 bits
Description
873