11Clock Generators; 12Legacy Power Management Theory Of Operation; 1Power Plane Control With Slp_S3#, 5.13.10.2Slp_S4# And Suspend-To-Ram Sequencing; 3Pwrok Signal - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

Functional Description
The SLP_S4# output signal is used to remove power to additional subsystems that are
powered during SLP_S3#.
SLP_S5# output signal can be used to cut power to the system core supply, as well as
power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done using the power supply, or by external FETs
on the motherboard.
SLP_A# output signal can be used to cut power to the Intel Management Engine, Clock
chip and SPI flash on a platform that support the M3 state.
SLP_LAN# output signal can be used to cut power to the external Intel 82579 GbE PHY
device.
5.13.10.2 SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The
SLP_S4# signal should be used to remove power to system memory rather than the
SLP_S5# signal. The SLP_S4# logic in the PCH provides a mechanism to fully cycle the
power to the DRAM and/or detect if the power is not cycled for a minimum time.
Note: To use the minimum DRAM power-down feature that is enabled by the SLP_S4#
Assertion Stretch Enable bit (D31:F0:A4h Bit 3), the DRAM power must be controlled
by the SLP_S4# signal.
5.13.10.3 PWROK Signal
When asserted, PWROK is an indication to the PCH that its core well power rails are
powered and stable. PWROK can be driven asynchronously. When PCH PWROK is low,
the PCH asynchronously asserts PLTRST#. PWROK must not glitch, even if RSMRST# is
low.
It is required that the power associated with PCI/PCIe have been valid for 99 ms prior
to PWROK assertion in order to comply with the 100 ms PCI 2.3 / PCIe 2.0 specification
on PLTRST# deassertion.
Note: SYS_RESET# is recommended for implementing the system reset button. This saves
external logic that is needed if the PWROK input is used. Additionally, it allows for
better handling of the SMBus and processor resets and avoids improperly reporting
power failures.
5.13.10.4 BATLOW# (Battery Low) (Mobile Only)
The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not
sufficient power. It also causes an SMI if the system is already in an S0 state.
5.13.11 Clock Generators
The clock generator is expected to provide the frequencies shown in
5.13.12 Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various
hardware mechanisms. The scheme relies on the concept of detecting when individual
subsystems are idle, detecting when the whole system is idle, and detecting when
accesses are attempted to idle subsystems.
Datasheet
Table 4-1.
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