Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 620

15.1.4 PCISTS — PCI Status Register (SATA–D31:F5)
Address Offset: 06h
Default Value:
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
15.1.5 RID—Revision Identification Register (SATA—D31:F5)
Offset Address: 08h
Default Value:
Bit
Revision ID — RO. See the Intel
7:0
of the RID Register.
620
07h
–
02B0h
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Master abort Not generated.
1 = SATA controller, as a master, generated a master abort.
Reserved
Signaled Target Abort (STA) — RO. Reserved as 0.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; Controls the device select time for the SATA controller's PCI interface.
Data Parity Error Detected (DPED) — R/WC. For PCH, this bit can only be set on
read completions received from SiBUS where there is a parity error.
1 = SATA controller, as a master, either detects a parity error or sees the parity error
line asserted, and the parity error response bit (bit 6 of the command register) is
set.
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66MHz Capable (66MHZ_CAP) — RO. Reserved as 1.
Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities
list. The minimum requirement for the capabilities list must be PCI power management
for the SATA controller.
Interrupt Status (INTS) — RO. Reflects the state of INTx# messages, IRQ14 or
IRQ15.
0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the
command register [offset 04h]).
1 = Interrupt is to be asserted
Reserved
See bit description
SATA Controller Registers (D31:F5)
Attribute:
Size:
Description
Attribute:
Size:
Description
®
6 Series Chipset Specification Update for the value
R/WC, RO
16 bits
RO
8 bits
Datasheet