Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 844

21.4.17 OPMENU—Opcode Menu Configuration Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Eight entries are available in this register to give GbE a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
Note: It is recommended that GbE avoid programming Write Enable opcodes in this menu.
Malicious software could then perform writes and erases to the SPI flash without using
the atomic cycle mechanism. This could cause functional failures in a shared flash
environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.
Bit
63:56 Allowable Opcode 7 — R/W. See the description for bits 7:0
55:48 Allowable Opcode 6 — R/W. See the description for bits 7:0
47:40 Allowable Opcode 5 — R/W. See the description for bits 7:0
39:32 Allowable Opcode 4 — R/W. See the description for bits 7:0
31:24 Allowable Opcode 3 — R/W. See the description for bits 7:0
23:16 Allowable Opcode 2 — R/W. See the description for bits 7:0
15:8 Allowable Opcode 1 — R/W. See the description for bits 7:0
Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use
7:0
when initiating SPI commands through the Control Register.
This register is not writable when the SPI Configuration Lock-Down bit (MBARB +
00h:15) is set.
844
MBARB + 98h
0000000000000000h
Description
§ §
Serial Peripheral Interface (SPI)
Attribute: R/W
Size: 64 bits
Datasheet