Lpc Interface Pci Register Address Map (Lpc I/F-D31:F0); Lpc Interface Bridge Registers (D31:F0) - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

LPC Interface Bridge Registers (D31:F0)

13 LPC Interface Bridge Registers
(D31:F0)
The LPC bridge function of the PCH resides in PCI Device 31:Function 0. This function
contains many other functional units, such as DMA and Interrupt controllers, Timers,
Power Management, System Management, GPIO, RTC, and LPC Configuration
Registers.
Registers and functions associated with other functional units are described in their
respective sections.
13.1 PCI Configuration Registers (LPC I/F—D31:F0)
Note: Address locations that are not shown should be treated as Reserved.
.
Table 13-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)
Offset
00h–01h
02h–03h
04h–05h
06h–07h
08h
09h
0Ah
0Bh
0Dh
0Eh
2Ch–2Fh
40h–43h
44h
48h–4Bh
4C
60h–63h
64h
68h–6Bh
6Ch–6Dh
70h–7F
80h
82h–83h
84h–87h
Datasheet
Mnemonic
VID Vendor Identification
DID Device Identification
PCICMD PCI Command
PCISTS PCI Status
RID Revision Identification
PI Programming Interface
SCC Sub Class Code
BCC Base Class Code
PLT Primary Latency Timer
HEADTYP Header Type
SS Sub System Identifiers
PMBASE ACPI Base Address
ACPI_CNTL ACPI Control
GPIOBASE GPIO Base Address
GC GPIO Control
PIRQ[n]_ROUT PIRQ[A–D] Routing Control
SIRQ_CNTL Serial IRQ Control
PIRQ[n]_ROUT PIRQ[E–H] Routing Control
LPC_IBDF IOxAPIC Bus:Device:Function
HPET Configuration
LPC_I/O_DEC I/O Decode Ranges
LPC_EN LPC I/F Enables
GEN1_DEC LPC I/F Generic Decode Range 1
Register Name Default Type
8086h RO
See register
RO
description
0007h R/W, RO
0210h R/WC, RO
See register
R/WO
description
00h RO
01h RO
06h RO
00h RO
80h RO
00000000h R/WO
00000001h R/W, RO
00h R/W
00000001h R/W, RO
00h R/W
80808080h R/W
10h R/W, RO
80808080h R/W
00F8h R/W
0000h R/W
0000h R/W
00000000h R/W
447