Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 545

LPC Interface Bridge Registers (D31:F0)
13.10.7 GP_SB_DATA—GP Serial Blink Data
Offset Address: GPIOBASE +24h
Default Value:
Lockable:
Bit
31:0
13.10.8 GPI_NMI_EN—GPI NMI Enable
Offset Address: GPIOBASE +28h
Default Value:
Lockable:
Bit
15:0
13.10.9 GPI_NMI_STS—GPI NMI Status
Offset Address: GPIOBASE +2Ah
Default Value:
Lockable:
Bit
15:0
Datasheet
00000000h
No
GP_SB_DATA[31:0] — R/W. This register contains the data serialized out. The
number of bits shifted out are selected through the DLS field in the GP_SB_CMDSTS
register. This register should not be modified by software when the Busy bit is set.
00000h
No
GPI_NMI_EN[15:0]. GPI NMI Enable: This bit only has effect if the
corresponding GPIO is used as an input and its GPI_ROUT register is being
programmed to NMI functionality. When set to 1, it used to allow active-low and
active-high inputs (depends on inversion bit) to cause NMI.
00000h
Yes
GPI_NMI_STS[15:0]. GPI NMI Status: GPI_NMI_STS[15:0]. GPI NMI Status:
This bit is set if the corresponding GPIO is used as an input, and its GPI_ROUT
register is being programmed to NMI functionality and also GPI_NMI_EN bit is set
when it detects either:
1) active-high edge when its corresponding GPI_INV is configured with value 0.
2) active-low edge when its corresponding GPI_INV is configured with value 1.
NOTE: Writing value of 1 will clear the bit, while writing value of 0 have no effect.
Attribute: R/W
Size: 32-bit
Power Well: Core
Description
Attribute: R/W
Size: 16-bit
Power Well: Core for 0:7
Resume for 8:15
Description
Attribute: R/WC
Size: 16-bit
Power Well: Core for 0:7
Resume for 8:15
Description
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