Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 105

PCH Pin States
Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations
(Sheet 5 of 6)
Signal Name
LVDSA_DATA[3:0],
LVDSA_DATA#[3:0]
LVDSA_CLK,
LVDSA_CLK#
LVDSB_DATA[3:0],
LVDSB_DATA#[3:0]
LVDSB_CLK,
LVDSB_CLK#
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
L_BKLTEN
L_BKLTCTL
L_CTRL_CLK
L_CTRL_DATA
LVD_VBG,
LVD_VREFH,
LVD_VREFL
CRT_RED,
CRT_GREEN,
CRT_BLUE
DAC_IREF
CRT_HSYNC
CRT_VSYNC
CRT_DDC_CLK
CRT_DDC_DATA
CRT_IRTN
FDI_FSYNC[1:0]
FDI_LSYNC[1:0]
FDI_INT
Datasheet
Power During Immediately
1
Plane Reset
LVDS Signals
Core High-Z
Core High-Z
Core High-Z
Core High-Z
Core High-Z
Core Low
Core Low
Core Low
Core Low
Core High-Z
Core High-Z
Core High-Z
Analog Display / CRT DAC Signals
Core High-Z
Core High-Z
Core Low
Core Low
Core High-Z
Core High-Z
Core High-Z
®
Intel Flexible Display Interface
Core High-Z
Core High-Z
Core High-Z
C-x
1
after Reset states
Defined/
High-Z
12
High-Z
Defined/
High-Z
12
High-Z
Defined/
High-Z
12
High-Z
Defined/
High-Z
12
High-Z
High-Z High-Z
High-Z High-Z
Low/
Low
12
High-Z
Low/
Low
12
High-Z
Low/
Low
12
High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z Defined
Low Low
Low Low
Low Low
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z Defined
High-Z Defined
High-Z Defined
S0/S1 S3 S4/S5
Defined/
Off
12
High-Z
Defined/
Off
12
High-Z
Defined/
Off
12
High-Z
Defined/
Off
12
High-Z
High-Z Off
High-Z Off
Low/
Off
12
High-Z
Low/
Off
12
High-Z
Low/
Off
12
High-Z
High-Z Off
High-Z Off
High-Z Off
Defined Off
Low Off
Low Off
Low Off
High-Z Off
High-Z Off
High-Z Off
Defined Off
Defined Off
Defined Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
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