Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 563

SATA Controller Registers (D31:F2)
14.1.25 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2)
Address Offset: 74h
Default Value:
Function Level Reset: No (Bits 8 and 15)
Bits
PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if
this bit and PMEE is set, a PME# will be generated from the SATA controller
NOTE: Whenever SCC = 01h, hardware will automatically change the attribute of this
15
This bit is not reset by Function Level Reset.
14:9 Reserved
PME Enable (PMEE) — R/W. When set, the SATA controller generates PME# form
D3
NOTE: Whenever SCCSCC = 01h, hardware will automatically change the attribute of
8
This bit is not reset by Function Level Reset.
7:4 Reserved
No Soft Reset (NSFRST) — RO. These bits are used to indicate whether devices
transitioning from D3
0 = Device transitioning from D3
1 = Device transitioning from D3
Configuration content is preserved. Upon transition from the D3
3
initialized state, no additional operating system intervention is required to preserve
configuration context beyond writing to the PowerState bits.
Regardless of this bit, the controller transition from D3
or bus segment reset will return to the state D0 uninitialized with only PME context
preserved if PME is supported and enabled.
2 Reserved
Power State (PS) — R/W. These bits are used both to determine the current power
state of the SATA controller and to set a new power state.
00 = D0 state
1:0
11 = D3
When in the D3
and memory spaces are not. Additionally, interrupts are blocked.
Datasheet
75h
–
0008h
bit to RO 0. Software is advised to clear PMEE and PMES together prior to
changing SCC thru MAP.SMS.
on a wake event.
HOT
this bit to RO 0. Software is advised to clear PMEE and PMES together prior to
changing SCC thru MAP.SMS.
state to D0 state will perform an internal reset.
HOT
state
HOT
state, the controller's configuration space is available, but the I/O
HOT
Attribute:
Size:
Description
state to D0 state perform an internal reset.
HOT
state to D0 state do not perform an internal reset.
HOT
state to D0 state by a system
HOT
R/W, R/WC
16 bits
state to D0 state
HOT
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