Sata Controller Pci Register Address Map (Sata-D31:F5) - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

SATA Controller Registers (D31:F5)
15 SATA Controller Registers
(D31:F5)
15.1 PCI Configuration Registers (SATA–D31:F5)
Note: Address locations that are not shown should be treated as Reserved.
All of the SATA registers are in the core well. None of the registers can be locked.
Table 15-1. SATA Controller PCI Register Address Map (SATA–D31:F5) (Sheet 1 of 2)
Offset
00h–01h
02h–03h
04h–05h
06h–07h
08h
09h
0Ah
0Bh
0Dh
10h–13h
14h–17h
18h–1Bh
1Ch–1Fh
20h–23h
24h–27h
2Ch–2Dh
2Eh–2Fh
34h
3Ch
3Dh
40h–41h
42h–43h
Datasheet
Mnemonic Register Name
VID Vendor Identification
DID Device Identification
PCICMD PCI Command
PCISTS PCI Status
RID Revision Identification
PI Programming Interface
SCC Sub Class Code
BCC Base Class Code
PMLT Primary Master Latency Timer
PCMD_BAR Primary Command Block Base Address
PCNL_BAR Primary Control Block Base Address
Secondary Command Block Base
SCMD_BAR
Address
SCNL_BAR Secondary Control Block Base Address
BAR Legacy Bus Master Base Address
Serial ATA Index / Data Pair Base
SIDPBA
Address
SVID Subsystem Vendor Identification
SID Subsystem Identification
CAP Capabilities Pointer
INT_LN Interrupt Line
INT_PN Interrupt Pin
IDE_TIM Primary IDE Timing Register
IDE_TIM Secondary IDE Timing Registers
Default Type
8086h RO
See register
RO
description
0000h R/W, RO
02B0h R/WC, RO
See register
RO
description
See
See register
register
description
description
See
See register
register
description
description
01h RO
00h RO
00000001h R/W, RO
00000001h R/W, RO
00000001h R/W, RO
00000001h R/W, RO
00000001h R/W, RO
See
00000000h register
description
0000h R/WO
0000h R/WO
80h RO
00h R/W
See register
RO
description
0000h R/W
0000h R/W
617