Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 815

Serial Peripheral Interface (SPI)
21.1.7 FRAP—Flash Regions Access Permissions Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: This register is only applicable when SPI device is in descriptor mode.
Bit
BIOS Master Write Access Grant (BMWAG) — R/W. Each bit [31:29] corresponds
to Master[7:0]. BIOS can grant one or more masters write access to the BIOS region 1
overriding the permissions in the Flash Descriptor.
31:24
Master[1] is Host processor/BIOS, Master[2] is Intel
is Host processor/GbE. Master[0] and Master[7:4] are reserved.
The contents of this register are locked by the FLOCKDN bit.
BIOS Master Read Access Grant (BMRAG) — R/W. Each bit [28:16] corresponds to
Master[7:0]. BIOS can grant one or more masters read access to the BIOS region 1
overriding the read permissions in the Flash Descriptor.
23:16
Master[1] is Host processor/BIOS, Master[2] is Intel
is Host processor/GbE. Master[0] and Master[7:4] are reserved.
The contents of this register are locked by the FLOCKDN bit
BIOS Region Write Access (BRWA) — RO. Each bit [15:8] corresponds to Regions
[7:0]. If the bit is set, this master can erase and write that particular region through
register accesses.
15:8
The contents of this register are that of the Flash Descriptor. Flash Master 1 Master
Region Write Access OR a particular master has granted BIOS write permissions in their
Master Write Access Grant register or the Flash Descriptor Security Override strap is
set.
BIOS Region Read Access (BRRA) — RO. Each bit [7:0] corresponds to Regions
[7:0]. If the bit is set, this master can read that particular region through register
accesses.
7:0
The contents of this register are that of the Flash Descriptor.Flash Master 1.Master
Region Write Access OR a particular master has granted BIOS read permissions in their
Master Read Access Grant register or the Flash Descriptor Security Override strap is
set.
Datasheet
SPIBAR + 50h
00000202h
Description
Attribute: RO, R/W
Size: 32 bits
®
Management Engine, Master[3]
®
Management Engine, Master[3]
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