Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 904

23.6.1 IDEDATA—IDE Data Register (IDER—D22:F2)
Address Offset: 0h
Default Value:
The IDE data interface is a special interface that is implemented in the HW. This data
interface is mapped to IO space from the host and takes read and write cycles from the
host targeting master or slave device.
Writes from host to this register result in the data being written to ME memory.
Reads from host to this register result in the data being fetched from ME memory.
Data is typically written/ read in WORDs. ME-FW must enable hardware to allow it to
accept Host initiated Read/ Write cycles, else the cycles are dropped.
Bit
7:0
23.6.2 IDEERD1—IDE Error Register DEV1
(IDER—D22:F2)
Address Offset: 01h
Default Value:
This register implements the Error register of the command block of the IDE function.
This register is read only by the HOST interface when DEV = 1 (slave device).
Bit
7:0
23.6.3 IDEERD0—IDE Error Register DEV0
(IDER—D22:F2)
Address Offset: 01h
Default Value:
This register implements the Error register of the command block of the IDE function.
This register is read only by the HOST interface when DEV = 0 (master device).
Bit
7:0
904
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
00h
IDE Data Register (IDEDR) — R/W. Data Register implements the data interface
for IDE. All writes and reads to this register translate into one or more corresponding
write/reads to ME memory
00h
IDE Error Data (IDEED) — R/W. Drive reflects its error/ diagnostic code to the host
using this register at different times.
00h
IDE Error Data (IDEED)— R/W. Drive reflects its error/ diagnostic code to the host
using this register at different times.
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
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