Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 518

Bit
11
10
9
8
7:6
5
4
3:1
0
518
Power Button Override Status (PWRBTNOR_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a Power Button Override occurs (that is, the power button is
pressed for at least 4 consecutive seconds), due to the corresponding bit in the
SMBus slave message, Intel ME Initiated Power Button Override, Intel ME Initiated
Host Reset with Power down or due to an internal thermal sensor catastrophic
condition. The power button override causes an unconditional transition to the S5
state. The BIOS or SCI handler clears this bit by writing a 1 to it. This bit is not
affected by hard resets using CF9h writes, and is not reset by RSMRST#. Thus, this
bit is preserved through power failures. Note that if this bit is still asserted when
the global SCI_EN is set then an SCI will be generated.
RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a
CF9 write, but is reset by DPWROK.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal).
Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting of the
RTC_STS bit will generate a wake event.
Reserved
Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard
resets caused by a CF9 write but is reset by DPWROK.
0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears
the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to
the S5 state with only PWRBTN# enabled as a wake event.
This bit can be cleared by software by writing a one to the bit position.
1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent
of any other enable bit.
In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or
SMI# if SCI_EN is not set) will be generated.
In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and
PWRBTN_STS are both set, a wake event is generated.
NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell
asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN# signal
must go inactive and active again to set the PWRBTN_STS bit.
Reserved
Global Status (GBL _STS) — R/WC.
0 = The SCI handler should then clear this bit by writing a 1 to the bit location.
1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI
handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and set
this bit.
Bus Master Status (BM_STS) — R/WC. This bit will not cause a wake event, SCI or
SMI#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by the PCH when a PCH-visible bus master requests access to memory or the
BM_BUSY# signal is active.
Reserved
Timer Overflow Status (TMROF_STS) — R/WC.
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered
from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit
(PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS bit will
additionally generate an SCI or SMI# (depending on the SCI_EN).
LPC Interface Bridge Registers (D31:F0)
Description
Datasheet