Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 741

SMBus Controller Registers (D31:F3)
18.1.4 PCISTS—PCI Status Register (SMBus—D31:F3)
Address:
Default Value:
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Detected Parity Error (DPE) — R/WC.
15 0 = No parity error detected.
1 = Parity error detected.
Signaled System Error (SSE) — R/WC.
14 0 = No system error detected.
1 = System error detected.
13 Received Master Abort (RMA) — RO. Hardwired to 0.
12 Received Target Abort (RTA) — RO. Hardwired to 0.
11 Signaled Target Abort (STA) — RO. Hardwired to 0.
DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for
DEVSEL# assertion for positive decode.
10:9
01 = Medium timing.
8 Data Parity Error Detected (DPED) — RO. Hardwired to 0.
7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
6 User Definable Features (UDF) — RO. Hardwired to 0.
5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list
4
structures in this function
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is
3
independent from the state of the Interrupt Enable bit in the PCI Command register.
2:0 Reserved
18.1.5 RID—Revision Identification Register (SMBus—D31:F3)
Offset Address: 08h
Default Value:
Bit
Revision ID — RO. See the Intel
7:0
of the RID Register.
Datasheet
06h 07h
–
0280h
See bit description
®
6 Series Chipset Specification Update for the value
Attributes: RO
Size: 16 bits
Description
Attribute: RO
Size: 8 bits
Description
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