Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 920

23.8.12 IDESBMDS1R—IDE Secondary Bus Master Device
Specific 1 Register (IDER—D22:F2)
Address Offset: 0Bh
Default Value:
Bit
7:0
23.8.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor
Table Pointer Byte 0 Register (IDER—D22:F2)
Address Offset: 0Ch
Default Value:
Bit
7:0
23.8.14 IDESBMDTPR1—IDE Secondary Bus Master Descriptor
Table Pointer Byte 1 Register (IDER—D22:F2)
Address Offset: 0Dh
Default Value:
Bit
7:0
920
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
00h
Device Specific Data1 (DSD1) — R/W. This register implements the bus master
Device Specific 1 register of the secondary channel. This register is programmed by
the Host for device specific data if any.
00h
Descriptor Table Pointer Byte 0 (DTPB0) — R/W. This register implements the
Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the secondary channel. This register is read/write by the HOST
interface.
00h
Descriptor Table Pointer Byte 1 (DTPB1) — R/W. This register implements the
Byte 1 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the secondary channel. This register is programmed by the Host.
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
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