Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 822

21.1.18 SSFS—Software Sequencing Flash Status Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: The Software Sequencing control and status registers are reserved if the hardware
sequencing control and status registers are used.
Bit
7:5 Reserved
Access Error Log (AEL) — RO. This bit reflects the value of the Hardware Sequencing
4
Status AEL register.
Flash Cycle Error (FCERR) — R/WC. Hardware sets this bit to 1 when a programmed
access is blocked from running on the SPI interface due to one of the protection policies
or when any of the programmed cycle registers is written while a programmed access is
3
already in progress. This bit remains asserted until cleared by software writing a 1 or
hardware reset due to a global reset or host partition reset in an Intel
system.
Cycle Done Status — R/WC. The PCH sets this bit to 1 when the SPI Cycle completes
(that is, SCIP bit is 0) after software sets the GO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset due to a global reset or host partition
2 reset in an Intel
is set, an internal signal is asserted to the SMI# generation block. Software must make
sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed
access.
1 Reserved
SPI Cycle In Progress (SCIP) — RO. Hardware sets this bit when software sets the
SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes
0 on the SPI interface. Hardware automatically sets and clears this bit so that software
can determine when read data is valid and/or when it is safe to begin programming the
next command. Software must only program the next command when this bit is 0.
822
SPIBAR + 90h
00h
Description
®
ME enabled system. When this bit is set and the SPI SMI# Enable bit
Serial Peripheral Interface (SPI)
Attribute: RO, R/WC
Size: 8 bits
®
ME enabled
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