Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 772

19.1.26 DCTL—Device Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 48h–49h
Default Value:
Bit
15 Reserved
14:12 Max Read Request Size (MRRS) — RO. Hardwired to 0.
Enable No Snoop (ENS) — RO. Not supported. The root port will never issue non-snoop
11
requests.
Aux Power PM Enable (APME) — R/W. The OS will set this bit to 1 if the device
10
connected has detected aux power. It has no effect on the root port otherwise.
9 Phantom Functions Enable (PFE) — RO. Not supported.
8 Extended Tag Field Enable (ETFE) — RO. Not supported.
Max Payload Size (MPS) — R/W. The root port only supports 128-B payloads,
7:5
regardless of the programming of this field.
4 Enable Relaxed Ordering (ERO) — RO. Not supported.
Unsupported Request Reporting Enable (URE) — R/W.
0 = The root port will ignore unsupported request errors.
1 = Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control
3
Fatal Error Reporting Enable (FEE) — R/W.
0 = The root port will ignore fatal errors.
2
1 = Enables signaling of ERR_FATAL to the Root Control register due to internally
Non-Fatal Error Reporting Enable (NFE) — R/W.
0 = The root port will ignore non-fatal errors.
1
1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally
Correctable Error Reporting Enable (CEE) — R/W.
0 = The root port will ignore correctable errors.
0
1 = Enables signaling of ERR_CORR to the Root Control register due to internally
772
0000h
register when detecting an unmasked Unsupported Request (UR). An ERR_COR is
signaled when a unmasked Advisory Non-Fatal UR is received. An ERR_FATAL,
ERR_or NONFATAL, is sent to the Root Control Register when an uncorrectable non-
Advisory UR is received with the severity set by the Uncorrectable Error Severity
register.
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
PCI Express* Configuration Registers
Attribute: R/W, RO
Size: 16 bits
Description
Datasheet