Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 392

10.1.46 OIC—Other Interrupt Control Register
Offset Address:
Default Value:
Bit
15:10
9
8
7:0
NOTE: FEC10000h–FEC3FFFFh is allocated to PCIe when I/OxApic Enable (PAE) bit is set.
392
31FE–31FFh
0000h
Reserved
Coprocessor Error Enable (CEN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the PCH generates IRQ13 internally and holds it until an I/O port
F0h write. It will also drive IGNNE# active.
APIC Enable (AEN) — R/W.
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
NOTE: Software should read this register after modifying APIC enable bit prior to
access to the IOxAPIC address range.
APIC Range Select (ASEL) — R/W. These bits define address bits 19:12 for the
IOxAPIC range. The default value of 00h enables compatibility with prior PCH products
as an initial value. This value must not be changed unless the IOxAPIC Enable bit is
cleared.
Chipset Configuration Registers
Attribute: R/W
Size: 16-bit
Description
Datasheet