Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 454

13.1.15 GC—GPIO Control Register (LPC I/F — D31:F0)
Offset Address: 4Ch
Default Value:
Bit
7:5 Reserved.
GPIO Enable (EN) — R/W. This bit enables/disables decode of the I/O range pointed
to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function.
4
0 = Disable.
1 = Enable.
3:1 Reserved.
GPIO Lockdown Enable (GLE) — R/W. This bit enables lockdown of the following
GPIO registers:
0
0 = Disable.
1 = Enable.
When this bit is written from 1-to-0, an SMI# is generated, if enabled. This ensures
that only SMM code can change the above GPIO registers after they are locked down.
454
00h
• Offset 00h: GPIO_USE_SEL
• Offset 04h: GP_IO_SEL
• Offset 0Ch: GP_LVL
• Offset 30h: GPIO_USE_SEL2
• Offset 34h: GP_IO_SEL2
• Offset 38h: GP_LVL2
• Offset 40h: GPIO_USE_SEL3
• Offset 44h: GP_IO_SEL3
• Offset 48h: GP_LVL3
• Offset 60h: GP_RST_SEL
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W
Size: 8 bit
Description
Datasheet