Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 752

18.2.9 RCV_SLVA—Receive Slave Address Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 09h
Default Value:
Lockable:
Bit
7 Reserved
SLAVE_ADDR — R/W. This field is the slave address that the PCH decodes for read and
write cycles. the default is not 0, so the SMBus Slave Interface can respond even before
6:0
the processor comes up (or if the processor is dead). This register is cleared by
RSMRST#, but not by PLTRST#.
18.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 0Ah–0Bh
Default Value:
Lockable:
This register contains the 16-bit data value written by the external SMBus master. The
processor can then read the value from this register. This register is reset by RSMRST#,
but not PLTRST#.
.
Bit
Data Message Byte 1 (DATA_MSG1) — RO. See
15:8
this field.
7:0
this field.
18.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 0Ch
Default Value:
Lockable:
.
Bit
7:2 Reserved
SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible
mode versus Advanced TCO mode.
1
0 = The PCH is in the compatible TCO mode.
1 = The PCH is in the advanced TCO mode.
CRC Error (CRCE) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set if a received message contained a CRC error. When this bit is set, the
0
752
44h
No
0000h
No
Data Message Byte 0 (DATA_MSG0) — RO. See
00h
No
DERR bit of the host status register will also be set. This bit will be set by the
controller if a software abort occurs in the middle of the CRC portion of the cycle or
an abort happens after the PCH has received the final data bit transmitted by an
external slave.
SMBus Controller Registers (D31:F3)
Attribute: R/W
Size: 8 bits
Power Well: Resume
Description
Attribute: RO
Size: 16 bits
Power Well: Resume
Description
Section 5.20.7
Section 5.20.7
Attribute: R/WC, RO
Size: 8 bits
Power Well: Resume
Description
for a discussion of
for a discussion of
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