Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 918

23.8.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor
Table Pointer Byte 1 Register (IDER—D22:F2)
Address Offset: 05h
Default Value:
Bit
7:0
23.8.7 IDEPBMDTPR2—IDE Primary Bus Master Descriptor
Table Pointer Byte 2 Register (IDER—D22:F2)
Address Offset: 06h
Default Value:
Bit
7:0
23.8.8 IDEPBMDTPR3—IDE Primary Bus Master Descriptor
Table Pointer Byte 3 Register (IDER—D22:F2)
Address Offset: 07h
Default Value:
Bit
7:0
918
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
00h
Descriptor Table Pointer Byte 1 (DTPB1) — R/W. This register implements the
Byte 1 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the primary channel. This register is programmed by the Host.
00h
Descriptor Table Pointer Byte 2 (DTPB2) — R/W. This register implements the
Byte 2 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the primary channel. This register is programmed by the Host.
00h
Descriptor Table Pointer Byte 3 (DTPB3) — R/W. This register implements the
Byte 3 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the primary channel. This register is programmed by the Host.
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Datasheet