Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 431

PCI-to-PCI Bridge Registers (D30:F0)
Bit
7
6
5
4:3
2
1
0
11.1.24 SVCAP—Subsystem Vendor Capability Register
(PCI-PCI—D30:F0)
Offset Address: 50h
Default Value:
Bit
15:8 Next Capability (NEXT) — RO. Value of 00h indicates this is the last item in the list.
Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge
7:0
subsystem vendor capability.
Datasheet
Subtractive Decode Policy (SDP) — R/W.
0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any
other device on the backbone (primary interface) to the PCI bus (secondary
interface).
1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the
corresponding Space Enable bit is set in the Command register.
NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI.
CMD.MSE BPC.SDP
0
0
1
1
PERR#-to-SERR# Enable (PSE) — R/W. When this bit is set, a 1 in the PERR#
Assertion status bit (in the Bridge Proprietary Status register) will result in an internal
SERR# assertion on the primary side of the bridge (if also enabled by the SERR#
Enable bit in the primary Command register). SERR# is a source of NMI.
Secondary Discard Timer Testmode (SDTT) — R/W.
0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E,
bit 9)
1 = The secondary discard timer will expire after 128 PCI clocks.
Reserved
Peer Decode Enable (PDE) — R/W.
0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O
cycles are not claimed.
1 = The PCI bridge will perform peer decode on any memory or I/O cycle from PCI that
falls outside of the memory and I/O window registers
Reserved
Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will
report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are
set, and CMD.SEE (D30:F0:04 bit 8) is set.
51h
–
000Dh
Description
Range
0 Don't Care
1 Don't Care
X Within range
X Outside
Attribute:
Size:
Description
Forwarding Policy
Forward unclaimed
cycles
Forwarding Prohibited
Positive decode and
forward
Subtractive decode &
forward
RO
16 bits
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