Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 630

15.1.27 SATACR0— SATA Capability Register 0 (SATA–D31:F5)
Address Offset: A8h–ABh
Default Value:
Function Level Reset: No (Bits 15:8 only)
Note: When SCC is 01h this register is read-only 0.
.
Bit
31:24 Reserved.
Major Revision (MAJREV) — RO. Major revision number of the SATA Capability
23:20
Pointer implemented.
Minor Revision (MINREV) — RO. Minor revision number of the SATA Capability
19:16
Pointer implemented.
15:8 Next Capability Pointer (NEXT) — R/WO. Points to the next capability structure.
Capability ID (CAP) — RO. The value of 12h has been assigned by the PCI SIG to
7:0
designate the SATA capability pointer.
15.1.28 SATACR1— SATA Capability Register 1 (SATA–D31:F5)
Address Offset: ACh–AFh
Default Value:
When SCC is 01h this register is read-only 0.
.
Bit
31:16 Reserved.
BAR Offset (BAROFST) — RO. Indicates the offset into the BAR where the index/Data
pair are located (in DWord granularity). The index and Data I/O registers are located at
15:4
offset 10h within the I/O space defined by LBAR (BAR4). A value of 004h indicates
offset 10h.
BAR Location (BARLOC) — RO. Indicates the absolute PCI Configuration Register
address of the BAR containing the Index/Data pair (in DWord granularity). The Index
3:0
and Data I/O registers reside within the space defined by LBAR (BAR4) in the SATA
controller. a value of 8h indicates and offset of 20h, which is LBAR (BAR4).
15.1.29 FLRCID— FLR Capability ID (SATA–D31:F5)
Address Offset: B0h–B1h
Default Value:
.
Bit
Next Capability Pointer — RO. A value of 00h indicates the final item in the Capability
15:8
List.
Capability ID — RO. The value of this field depends on the FLRCSSECL bit.
7:0 If FLRCSSEL = 0, this field is 13h
If FLRCSSEL = 1, this field is 09h, indicating vendor specific capability.
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0010B012h
00000048h
0009h
SATA Controller Registers (D31:F5)
Attribute: RO, R/WO
Size: 32 bits
Description
Attribute: RO
Size: 32 bits
Description
Attribute: RO
Size: 16 bits
Description
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