Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 66

Table 2-8. Power Management Interface Signals (Sheet 4 of 4)
Name
SUS_STAT# /
GPIO61
SUSCLK /GPIO62
SUSWARN# /
SUSPWRDNACK /
GPIO30
SUSPWRDNACK /
SUSWARN# /
GPIO30
SYS_PWROK
SYS_RESET#
WAKE#
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Type
Suspend Status: This signal is asserted by the PCH to indicate
that the system will be entering a low power state soon. This can
be monitored by devices with memory that need to switch from
normal refresh to suspend refresh mode. It can also be used by
O
other peripherals as an indication that they should isolate their
outputs that may be going to powered-off planes.
Pin may also be used as GPIO61.
Suspend Clock: This clock is an output of the RTC generator
circuit to use by other chips for refresh clock.
O
Pin may also be used as GPIO62.
SUSWARN#: This pin asserts low when the PCH is planning to
enter the Deep S4/S5 power state and remove Suspend power
(using SLP_SUS#). The EC/motherboard controlling logic must
observe edges on this pin, preparing for SUS well power loss on a
falling edge and preparing for SUS well related activity (host/Intel
ME wakes and runtime events) on a rising edge. SUSACK# must be
driven to match SUSWARN# once the above preparation is
complete. SUSACK# should be asserted within a minimal amount
of time from SUSWARN# assertion as no wake events are
O
supported if SUSWARN# is asserted but SUSACK# is not asserted.
Platforms supporting Deep S4/S5, but not wishing to participate in
the handshake during wake and Deep S4/S5 entry may tie
SUSACK# to SUSWARN#.
This pin may be muxed with a GPIO for use in systems that do not
support Deep S4/S5. This pin is muxed with SUSPWRDNACK since
it is not needed in Deep S4/S5 supported platforms.
Reset type: RSMRST#
This signal is multiplexed with GPIO30 and SUSPWRDNACK.
SUSPWRDNACK: Active high. Asserted by the PCH on behalf of
the Intel ME when it does not require the PCH Suspend well to be
powered.
O
Platforms are not expected to use this signal when the PCH's Deep
S4/S5 feature is used.
This signal is multiplexed with GPIO30 and SUSWARN#.
System Power OK: This generic power good input to the PCH is
driven and utilized in a platform-specific manner. While PWROK
always indicates that the core wells of the PCH are stable,
I
SYS_PWROK is used to inform the PCH that power is stable to
some other system component(s) and the system is ready to start
the exit from reset.
System Reset: This pin forces an internal reset after being
debounced. The PCH will reset immediately if the SMBus is idle;
I
otherwise, it will wait up to 25 ms ±2 ms for the SMBus to idle
before forcing a reset on the system.
PCI Express* Wake Event: Sideband wake signal on PCI Express
I
asserted by components requesting wake up.
Signal Description
Description
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