Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 445

Gigabit LAN Configuration Registers
12.1.29 FLRCLV—Function Level Reset Capability Length and
Version
(Gigabit LAN—D25:F0)
Address Offset: E2h–E3h
Default Value:
Function Level Reset: No (Bits 9:8 Only When FLRCSSEL = 0)
When FLRCSSEL = 0, this register is defined as follows:
Bit
15:10
9
8
7:0
When FLRCSSEL = 1, this register is defined as follows:
Bit
15:12
11:8
7:0
12.1.30 DEVCTRL—Device Control (Gigabit LAN—D25:F0)
Address Offset: E4–E5h
Default Value:
Bit
15:9
8
7:1
0
Datasheet
See Description.
Reserved.
Function Level Reset Capability — R/WO.
1 = Support for Function Level Reset.
This bit is not reset by Function Level Reset.
TXP Capability — R/WO.
1 = Indicates support for the Transactions Pending (TXP) bit. TXP must be supported if
FLR is supported.
Capability Length — RO. The value of this field indicates the number of bytes of the
vendor specific capability as require by the PCI specification. It has the value of 06h for
the Function Level Reset capability.
Vendor Specific Capability ID — RO. A value of 2h in this field identifies this
capability as Function Level Reset.
Capability Version— RO. The value of this field indicates the version of the Function
Level Reset Capability. Default is 0h.
Capability Length — RO. The value of this field indicates the number of bytes of the
vendor specific capability as require by the PCI specification. It has the value of 06h for
the Function Level Reset capability.
0000h
Reserved.
Transactions Pending (TXP) — R/W.
1 = Indicates the controller has issued Non-Posted requests which have not been
completed.
0 = Indicates that completions for all Non-Posted requests have been received.
Reserved
Initiate Function Level Reset — RO. This bit is used to initiate an FLT transition. A
write of 1 initiates the transition. Since hardware must not respond to any cycles until
Function Level Reset completion, the value read by software from this bit is 0.
Attribute: R/WO, RO
Size: 16 bits
Description
Description
Attribute: R/W, RO
Size: 16 bits
Description
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