Signal Description - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

Signal Description

2 Signal Description
This chapter provides a detailed description of each signal. The signals are arranged in
functional groups according to their associated interface.
The "#" symbol at the end of the signal name indicates that the active, or asserted
state occurs when the signal is at a low voltage level. When "#" is not present, the
signal is asserted when at the high voltage level.
The following notations are used to describe the signal type:
I
O
OD O
I/OD
I/O
CMOS
COD
HVCMOS
A
The "Type" for each signal is indicative of the functional operating mode of the signal.
Unless otherwise noted in
functional operating mode after RTCRST# deasserts for signals in the RTC well, after
RSMRST# deasserts for signals in the suspend well, after PWROK asserts for signals in
the core well, after DPWROK asserts for Signals in the Deep S4/S5 well, after APWROK
asserts for Signals in the Active Sleep well.
Datasheet
Input Pin
Output Pin
Open Drain Output Pin.
Bi-directional Input/Open Drain Output Pin.
Bi-directional Input/Output Pin.
CMOS buffers. 1.5 V tolerant.
CMOS Open Drain buffers. 3.3 V tolerant.
High Voltage CMOS buffers. 3.3 V tolerant.
Analog reference or output.
Section 3.2 or Section 3.3, a signal is considered to be in the
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