Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 675

EHCI Controller Registers (D29:F0, D26:F0)
Bit
Port Test Control — R/W. When this field is 0s, the port is NOT operating in a test
mode. A non-zero value indicates that it is operating in test mode and the specific test
mode is indicated by the specific value. The encoding of the test mode bits are (0110b –
1111b are reserved):
19:16
Refer to the USB Specification Revision 2.0, Chapter 7 for details on each test mode.
15:14 Reserved.
Port Owner — R/W. This bit unconditionally goes to a 0 when the Configured Flag bit in
the USB2.0_CMD register makes a 0 to 1 transition.
System software uses this field to release ownership of the port to a selected host
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controller (in the event that the attached device is not a high-speed device). Software
writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit
means that a companion host controller owns and controls the port. See Section 4 of the
EHCI Specification for operational details.
Port Power (PP) — RO. Read-only with a value of 1. This indicates that the port does
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have power.
Line Status— RO.These bits reflect the current logical levels of the D+ (bit 11) and D–
(bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to
the port reset and enable sequence. This field is valid only when the port enable bit is 0
and the current connect status bit is set to a 1.
11:10
00 = SE0
10 = J-state
01 = K-state
11 = Undefined
9 Reserved.
Datasheet
Value Maximum Interrupt Interval
0000b Test mode not enabled (default)
0001b
0010b
0011b
0100b
0101b
Description
Test J_STATE
Test K_STATE
Test SE0_NAK
Test Packet
FORCE_ENABLE
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