Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 543

LPC Interface Bridge Registers (D31:F0)
13.10.3 GP_LVL—GPIO Level for Input or Output Register
Offset Address: GPIOBASE +0Ch
Default Value:
Lockable:
Bit
31:0
13.10.4 GPO_BLINK—GPO Blink Enable Register
Offset Address: GPIOBASE +18h
Default Value:
Lockable:
Bit
31:0
NOTE: GPIO18 will blink by default immediately after reset. This signal could be connected to an
LED to indicate a failed boot (by programming BIOS to clear GP_BLINK18 after successful
POST).
Datasheet
02FE0100h
Yes
GP_LVL[31:0]— R/W. These registers are implemented as dual read/write with
dedicated storage each. Write value will be stored in the write register, while read is
coming from the read register which will always reflect the value of the pin.
If GPIO[n] is programmed to be an output (using the corresponding bit in the
GP_IO_SEL register), then the corresponding GP_LVL[n] write register value will
drive a high or low value on the output pin. 1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are
stored but have no effect to the pin value. The value reported in this register is
undefined when programmed as native mode.
NOTE: Bit 29 setting will be ignored if Intel ME FW is configuring SLP_LAN# behavior.
When GPIO29/SLP_LAN# Select Soft-strap is set to 1 (GPIO usage), bit 29
can be used as regular GP_LVL bit.
00040000h
No
GP_BLINK[31:0] — R/W. The setting of this bit has no effect if the corresponding
GPIO signal is programmed as an input.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will
blink at a rate of approximately once per second. The high and low times have
approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is
set.
The value of the corresponding GP_LVL bit remains unchanged during the blink
process, and does not effect the blink in any way. The GP_LVL bit is not altered
when programmed to blink. It will remain at its previous value.
These bits correspond to GPIO in the Resume well. These bits revert to the default
value based on RSMRST# or a write to the CF9h register (but not just on
PLTRST#).
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
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