Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 362

Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 4 of 4)
Offset
–
3A80 3A83h
–
3A84 3A87h
–
3A88 3A8Bh
10.1.1 CIR0—Chipset Initialization Register 0
Offset Address: 0050–0053h
Default Value:
Bit
31
30:0
362
Mnemonic
CIR27 Chipset Initialization Register 27
CIR28 Chipset Initialization Register 28
CIR29 Chipset Initialization Register 29
00000000h
TC Lock-Down (TCLOCKDN)— R/WL. When set to 1, certain DMI configuration
registers are locked down by this and cannot be written. Once set to 1, this bit can
only be cleared by a PLTRST#.
CIR0 Field 0— R/WL. BIOS must set this field. Bits locked by TCLOCKDN.
Chipset Configuration Registers
Register Name
Attribute:
Size:
Description
Default Type
00000000h R/W
00000000h R/W
00000000h R/W
R/WL
32-bit
Datasheet