Apic Direct Registers; Apic Indirect Registers - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

LPC Interface Bridge Registers (D31:F0)
13.5 Advanced Programmable Interrupt Controller
(APIC)
13.5.1 APIC Register Map
The APIC is accessed using an indirect addressing scheme. Two registers are visible by
software for manipulation of most of the APIC registers. These registers are mapped
into memory space. The address bits 19:12 of the address range are programmable
through bits 7:0 of OIC register (Chipset Config Registers:Offset 31FEh) The registers
are shown in
Table 13-4. APIC Direct Registers
Table 13-5
Register. When accessing these registers, accesses must be done one DWord at a time.
For example, software should never access byte 2 from the Data register before
accessing bytes 0 and 1. The hardware will not attempt to recover from a bad
programming model in this case.
Table 13-5. APIC Indirect Registers
Index
00
01
02–0F
10–11
12–13
...
3E–3F
40–FF
13.5.2 IND—Index Register
Memory Address FEC
Default Value:
The Index Register will select which APIC indirect register to be manipulated by
software. The selector values for the indirect registers are listed in
will program this register to select the desired APIC internal register
.
Bit
7:0 APIC Index — R/W. This is an 8-bit pointer into the I/O APIC register table.
Datasheet
Table 13-4.
Address Mnemonic
FEC_ _0000h
FEC_ _0010h
FEC_ _0040h
lists the registers which can be accessed within the APIC using the Index
Mnemonic
ID Identification
VER Version
— Reserved
REDIR_TBL0 Redirection Table 0
REDIR_TBL1 Redirection Table 1
... ...
REDIR_TBL23 Redirection Table 23
— Reserved
0000h
_ _
00hSize:
Register Name
IND Index
DAT Data
EOIR EOI
Register Name
Attribute:
8 bits
Description
Size Type
8 bits R/W
32 bits R/W
32 bits WO
Size Type
32 bits R/W
32 bits RO
— RO
64 bits R/W, RO
64 bits R/W, RO
... ...
64 bits R/W, RO
— RO
R/W
Table 13-5. Software
493