Page 1 ® Intel 6 Series Chipset Datasheet January 2011 Document Number: 324645-001...
Page 2 Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses.
Page 3: Table Of Contents
LVDS Signals ....................74 2.21 Analog Display /VGA DAC Signals ................ 75 ® ® 2.22 Intel Flexible Display Interface (Intel FDI) ............76 2.23 Digital Display Signals..................77 2.24 General Purpose I/O Signals ................80 2.25 Manageability Signals ..................84 2.26...
Page 4 5.2.4.4 SMI/SCI Generation..............122 Gigabit Ethernet Controller (B0:D25:F0) ............. 122 5.3.1 GbE PCI Express* Bus Interface.............. 124 5.3.1.1 Transaction Layer..............124 5.3.1.2 Data Alignment ............... 124 5.3.1.3 Configuration Request Retry Status ........... 124 5.3.2 Error Events and Error Reporting ............124 5.3.2.1 Data Parity Error ..............
Page 5 5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)......147 5.8.4.4 Specific Rotation Mode (Specific Priority)........147 5.8.4.5 Poll Mode................147 5.8.4.6 Cascade Mode ................ 148 5.8.4.7 Edge and Level Triggered Mode ..........148 5.8.4.8 End of Interrupt (EOI) Operations ..........148 5.8.4.9 Normal End of Interrupt............
Page 6 5.16.5 Hot Plug Operation................191 5.16.5.1 Low Power Device Presence Detection ........191 5.16.6 Function Level Reset Support (FLR) ............192 5.16.6.1 FLR Steps................192 ® 5.16.7 Intel Rapid Storage Technology Configuration......... 192 ® 5.16.7.1 Intel Rapid Storage Manager RAID Option ROM ......193 5.16.8 Power Management Operation ..............
Page 7 5.21.2 Thermal Reporting Over System Management Link 1 Interface (SMLink1) ..229 5.21.2.1 Supported Addresses............... 230 ® 5.21.2.2 I C Write Commands to the Intel ME ........231 5.21.2.3 Block Read Command.............. 231 5.21.2.4 Read Data Format..............233 5.21.2.5 Thermal Data Update Rate ............233 5.21.2.6 Temperature Comparator and Alert ...........
Page 8 5.24.4 Serial Flash Device Compatibility Requirements ........247 5.24.4.1 PCH SPI Based BIOS Requirements..........248 5.24.4.2 Integrated LAN Firmware SPI Flash Requirements......248 ® 5.24.4.3 Intel Management Engine Firmware SPI Flash Requirements ..248 5.24.4.4 Hardware Sequencing Requirements .......... 249 5.24.5 Multiple Page Write Usage Model............. 250 5.24.5.1 Soft Flash Protection..............
Page 9 Register and Memory Mapping................349 PCI Devices and Functions................350 PCI Configuration Map ..................351 I/O Map ......................351 9.3.1 Fixed I/O Address Ranges ..............351 9.3.2 Variable I/O Decode Ranges ..............354 Memory Map....................355 9.4.1 Boot-Block Update Scheme..............357 Chipset Configuration Registers................
Page 10 10.1.55CIR33—Chipset Initialization Register 33..........396 10.1.56CIR34—Chipset Initialization Register 34..........396 10.1.57CIR12—Chipset Initialization Register 12..........397 10.1.58CIR14—Chipset Initialization Register 14..........397 10.1.59CIR15—Chipset Initialization Register 15..........397 10.1.60CIR13—Chipset Initialization Register 13..........397 10.1.61CIR16—Chipset Initialization Register 16..........397 10.1.62CIR18—Chipset Initialization Register 18..........397 10.1.63CIR17—Chipset Initialization Register 17..........
Page 11 11.1.22BPS—Bridge Proprietary Status Register (PCI-PCI—D30:F0) ................429 11.1.23BPC—Bridge Policy Configuration Register (PCI-PCI—D30:F0) ................430 11.1.24SVCAP—Subsystem Vendor Capability Register (PCI-PCI—D30:F0) ................431 11.1.25SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) ......432 Gigabit LAN Configuration Registers ..............433 12.1 Gigabit LAN Configuration Registers (Gigabit LAN — D25:F0)................... 433 12.1.1 VID—Vendor Identification Register (Gigabit LAN—D25:F0)................
Page 12 12.1.29FLRCLV—Function Level Reset Capability Length and Version (Gigabit LAN—D25:F0) ................445 12.1.30DEVCTRL—Device Control (Gigabit LAN—D25:F0) ........445 LPC Interface Bridge Registers (D31:F0) ............... 447 13.1 PCI Configuration Registers (LPC I/F—D31:F0) ............ 447 13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ......448 13.1.2 DID—Device Identification Register (LPC I/F—D31:F0).......
Page 13 13.1.38.3FVEC2—Feature Vector Register 2 ..........472 13.1.38.4FVEC3—Feature Vector Register 3 ..........473 13.1.39RCBA—Root Complex Base Address Register (LPC I/F—D31:F0) ................473 13.2 DMA I/O Registers................... 474 13.2.1 DMABASE_CA—DMA Base and Current Address Registers ......475 13.2.2 DMABASE_CC—DMA Base and Current Count Registers ......476 13.2.3 DMAMEM_LP—DMA Memory Low Page Registers ........
Page 14 13.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration Lock Register................512 13.8.1.5 Chipset Initialization Register 4 (PM—D31:F0)......512 13.8.1.6 BM_BREAK_EN Register #2(PM—D31:F0) ........513 13.8.1.7 BM_BREAK_EN Register (PM—D31:F0) ........513 13.8.1.8 PMIR—Power Management Initialization Register (PM—D31:F0)..514 13.8.1.9 GPIO_ROUT—GPIO Routing Control Register (PM—D31:F0) ................. 514 13.8.2 APM I/O Decode ...................
Page 15 14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h ..556 14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h ..556 14.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ........556 14.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–D31:F2) ..............556 14.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2)..................
Page 16 14.3.2.3 PxSERR—Serial ATA Error Register (D31:F2)....... 586 14.4 AHCI Registers (D31:F2) .................. 588 14.4.1 AHCI Generic Host Control Registers (D31:F2).......... 589 14.4.1.1 CAP—Host Capabilities Register (D31:F2) ........590 14.4.1.2 GHC—Global PCH Control Register (D31:F2) ....... 592 14.4.1.3 IS—Interrupt Status Register (D31:F2) ........593 14.4.1.4 PI—Ports Implemented Register (D31:F2) ........
Page 17 15.1.23PC—PCI Power Management Capabilities Register (SATA–D31:F5)..................626 15.1.24PMCS—PCI Power Management Control and Status Register (SATA–D31:F5) ............... 627 15.1.25MAP—Address Map Register (SATA–D31:F5) ..........628 15.1.26PCS—Port Control and Status Register (SATA–D31:F5)......629 15.1.27SATACR0— SATA Capability Register 0 (SATA–D31:F5) ......630 15.1.28SATACR1— SATA Capability Register 1 (SATA–D31:F5) ......630 15.1.29FLRCID—...
Page 18 16.1.27LEG_EXT_CAP—USB EHCI Legacy Support Extended Capability Register (USB EHCI—D29:F0, D26:F0)........654 16.1.28LEG_EXT_CS—USB EHCI Legacy Support Extended Control / Status Register (USB EHCI—D29:F0, D26:F0) ......655 16.1.29SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F0, D26:F0)..............657 16.1.30ACCESS_CNTL—Access Control Register (USB EHCI—D29:F0, D26:F0)..............658 16.1.31EHCIIR1—EHCI Initialization Register 1...
Page 19 17.1.1.2 DID—Device Identification Register ® (Intel High Definition Audio Controller—D27:F0) ....... 685 17.1.1.3 PCICMD—PCI Command Register ® (Intel High Definition Audio Controller—D27:F0) ....... 686 17.1.1.4 PCISTS—PCI Status Register ® (Intel High Definition Audio Controller—D27:F0) ....... 687 17.1.1.5 RID—Revision Identification Register ®...
Page 20 High Definition Audio Controller—D27:F0)......705 17.1.1.51L1ADDU—Link 1 Upper Address Register ® (Intel High Definition Audio Controller—D27:F0)......705 ® 17.1.2 Intel High Definition Audio Memory Mapped Configuration Registers ® (Intel High Definition Audio D27:F0) ............. 706 17.1.2.1 GCAP—Global Capabilities Register ®...
Page 21 17.1.2.36SDSTS—Stream Descriptor Status Register ® (Intel High Definition Audio Controller—D27:F0) ....... 727 17.1.2.37SDLPIB—Stream Descriptor Link Position in Buffer ® Register (Intel High Definition Audio Controller—D27:F0) ... 728 17.1.2.38SDCBL—Stream Descriptor Cyclic Buffer Length Register ® (Intel High Definition Audio Controller—D27:F0) ....... 728 17.1.2.39SDLVI—Stream Descriptor Last Valid Index Register...
Page 22 18.1.1 VID—Vendor Identification Register (SMBus—D31:F3) ....... 739 18.1.2 DID—Device Identification Register (SMBus—D31:F3) ....... 740 18.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) ........740 18.1.4 PCISTS—PCI Status Register (SMBus—D31:F3) ........741 18.1.5 RID—Revision Identification Register (SMBus—D31:F3) ......741 18.1.6 PI—Programming Interface Register (SMBus—D31:F3) ......742 18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3) ........
Page 23 19.1.8 BCC—Base Class Code Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)....... 762 19.1.9 CLS—Cache Line Size Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)....... 763 19.1.10PLT—Primary Latency Timer Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)....... 763 19.1.11HEADTYP—Header Type Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)....... 763 19.1.12BNUM—Bus Number Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)....... 764 19.1.13SLT—Secondary Latency Timer (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)....... 764 19.1.14IOBL—I/O Base and Limit Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7).......
Page 24 19.1.41MA—Message Signaled Interrupt Message Address Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ......784 19.1.42MD—Message Signaled Interrupt Message Data Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........784 19.1.43SVCAP—Subsystem Vendor Capability Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........784 19.1.44SVID—Subsystem Vendor Identification Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........784 19.1.45PMCAP—Power Management Capability Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........
Page 25 (SPI Memory Mapped Configuration Registers) ......... 816 21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register (SPI Memory Mapped Configuration Registers) ......... 816 21.1.10FREG2—Flash Region 2 (Intel® ME) Register (SPI Memory Mapped Configuration Registers) ......... 817 21.1.11FREG3—Flash Region 3 (GbE) Register (SPI Memory Mapped Configuration Registers) ......... 817 21.1.12FREG4—Flash Region 4 (Platform Data) Register...
Page 26 (GbE LAN Memory Mapped Configuration Registers) ........838 21.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register (GbE LAN Memory Mapped Configuration Registers) ........838 21.4.9 FREG2—Flash Region 2 (Intel® ME) Register (GbE LAN Memory Mapped Configuration Registers) ........838 21.4.10FREG3—Flash Region 3 (GbE) Register (GbE LAN Memory Mapped Configuration Registers) ........
Page 27 ® Intel Management Engine Interface (MEI) Subsystem Registers (D22:F0) ..867 ® 23.1 First Intel Management Engine Interface (Intel MEI) Configuration Registers (MEI — D22:F0)....................867 23.1.1 VID—Vendor Identification Register (MEI—D22:F0)..................868 23.1.2 DID—Device Identification Register (MEI—D22:F0)..................868 23.1.3 PCICMD—PCI Command Register (MEI—D22:F0)..................
Page 28 23.1.27HERX—MEI Extend Register DWX (MEI—D22:F0) ..................878 23.2 Second Management Engine Interface(MEI1) Configuration Registers (MEI—D22:F1) ....................879 23.2.1 VID—Vendor Identification Register (MEI—D22:F1) ..................880 23.2.2 DID—Device Identification Register (MEI—D22:F1) ..................880 23.2.3 PCICMD—PCI Command Register (MEI—D22:F1) ..................880 23.2.4 PCISTS—PCI Status Register (MEI—D22:F1) ..................
Page 29 23.4.1 H_CB_WW—Host Circular Buffer Write Window (MEI MMIO Register) ................891 23.4.2 H_CSR—Host Control Status (MEI MMIO Register) ................892 23.4.3 ME_CB_RW—ME Circular Buffer Read Window (MEI MMIO Register) ................892 23.4.4 ME CSR_HA—ME Control Status Host Access (MEI MMIO Register) ................893 23.5 IDE Function for Remote Boot and Installations PT IDER Registers (IDER —...
Page 30 23.6.11IDECLIR—IDE Cylinder Low In Register Register (IDER—D22:F2) ................... 908 23.6.12IDCLOR1—IDE Cylinder Low Out Register Device 1 Register (IDER—D22:F2) ............... 908 23.6.13IDCLOR0—IDE Cylinder Low Out Register Device 0 Register (IDER—D22:F2) ............... 909 23.6.14IDCHOR0—IDE Cylinder High Out Register Device 0 Register (IDER—D22:F2) ............... 909 23.6.15IDCHOR1—IDE Cylinder High Out Register Device 1 Register (IDER—D22:F2) ...............
Page 31 23.9.7 CLS—Cache Line Size Register (KT—D22:F3) ........... 925 23.9.8 KTIBA—KT IO Block Base Address Register (KT—D22:F3) ..................925 23.9.9 KTMBA—KT Memory Block Base Address Register (KT—D22:F3) ..................925 23.9.10SVID—Subsystem Vendor ID Register (KT—D22:F3) ......... 926 23.9.11SID—Subsystem ID Register (KT—D22:F3)..........926 23.9.12CAP—Capabilities Pointer Register (KT—D22:F3) ........
Page 32 SMBus Transaction ..................... 342 8-21 SMBus Timeout....................342 8-22 SPI Timings ....................... 343 ® 8-23 Intel High Definition Audio Input and Output Timings ..........343 8-24 Dual Channel Interface Timings................344 8-25 Dual Channel Interface Timings................344 8-26 LVDS Load and Transition Times ................344 8-27 Transmitting Position (Data to Strobe) ..............
Page 33 Tables Industry Specifications ..................41 ® Desktop Intel 6 Series Chipset SKUs ..............51 ® Mobile Intel 6 Series Chipset SKUs............... 52 Direct Media Interface Signals ................55 PCI Express* Signals.................... 55 PCI Interface Signals.................... 56 Serial ATA Interface Signals .................. 58 LPC Interface Signals ...................
Page 34 Data Values for Slave Read Registers..............225 5-52 Host Notify Format ..................... 227 5-53 C Write Commands to the Intel ME ..............231 5-54 Block Read Command – Byte Definition ..............232 5-55 Region Size versus Erase Granularity of Flash Components ........244 5-56 Region Access Control Table ................
Page 35 Controller Link Receive Timings ................330 8-36 Power Sequencing and Reset Signal Timings............331 PCI Devices and Functions .................. 350 ® Fixed I/O Ranges Decoded by Intel PCH.............. 352 Variable I/O Decode Ranges ................354 Memory Decode Ranges from Processor Perspective ..........355 10-1 Chipset Configuration Register Memory Map (Memory Space) ........
Page 36 23-5 IDE BAR0 Register Address Map ................903 23-6 IDE BAR4 Register Address Map ................915 23-7 Serial Port for Remote Keyboard and Text (KT) Redirection Register Address Map...................... 922 23-8 KT IO/ Memory Mapped Device Register Address Map ..........929 Datasheet...
Page 37 Revision History Revision Description Date • Initial Release January 2011 Datasheet...
Page 38 — NEW: Data transfer rates up to 6.0 Gb/s — Jumbo Frame Support (600 MB/s) on up to two ports ® ® Intel I/O Virtualization (Intel VT-d) Support  ® — Data transfer rates up to 3.0 Gb/s Intel Trusted Execution Technology Support ...
Page 39 External Glue Integration Serial Peripheral Interface (SPI)   — Integrated Pull-down and Series resistors — Supports up to two SPI devices on USB — Supports 20 MHz, 33 MHz, and 50 MHz SPI devices Enhanced DMA Controller  — Two cascaded 8237 DMA controllers —...
Page 40 Datasheet...
Page 41: Introduction
SKUs). Note: Throughout this document, Platform Controller Hub (PCH) is used as a general term and refers to all Intel 6 Series Chipset SKUs, unless specifically noted otherwise. Note: Throughout this document, the terms “Desktop” and “Desktop Only” refer to ®...
Page 42 IEEE 802.3 Fast Ethernet getieee802/ AT Attachment - 6 with Packet Interface (ATA/ATAPI - http://T13.org (T13 1410D) IA-PC HPET (High Precision Event Timers) Specification, http://www.intel.com/ Revision 1,0a hardwaredesign/hpetspec_1.pdf http:// TPM Specification 1.02, Level 2 Revision 103 www.trustedcomputinggroup.org/ specs/TPM http://www.intel.com/technology/...
Page 43 Chapter 17, “Integrated Intel® High Definition Audio Controller Registers” Chapter 17 provides a detailed description of registers that reside in the Intel High Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0). Chapter 18, “SMBus Controller Registers (D31:F3)”...
Page 44: Overview
® ® • Supports Intel Rapid Storage Technology (Intel RST) ® ® • Supports Intel Virtualization Technology for Directed I/O (Intel VT-d) ® ® • Supports Intel Trusted Execution Technology (Intel TXT) • Integrated Clock Controller • Analog and Digital Display ports —...
Page 45: Capability Overview
PCH. The display data from the frame buffer is processed by the display engine and sent to the PCH where it is transcoded and driven out on the panel. Intel FDI involves two channels – A and B for display data transfer.
Page 46 Intel Rapid Storage Technology The PCH provides support for Intel Rapid Storage Technology, providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6 SATA ports of the PCH.
Page 47 Introduction The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH’s DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface.
Page 48 PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt. • Function Disable. The PCH provides the ability to disable the following integrated functions: LAN, USB, LPC, Intel HD Audio, SATA, PCI Express or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space.
Page 49 With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver CE levels of audio experience. On the input side, the PCH adds support for an array of microphones.
Page 50 Introduction Integrated Clock Controller The PCH contains a Fully Integrated Clock Controller (ICC) generating various platform clocks from a 25 MHz crystal source. The ICC contains up to eight PLLs and four Spread Modulators for generating various clocks suited to the platform needs. The ICC supplies up to ten 100 MHz PCI Express 2.0 Specification compliant clocks, one 100 MHz BCLK/ DMI to the processor, one 120 MHz for embedded DisplayPort on the processor, four 33 MHz clocks for SIO/EC/LPC/TPM devices and four Flex Clocks that can be configured...
Page 51: Intel ® 6 Series Chipset Sku Definition
Intel NOTES: Contact your local Intel Field Sales Representative for currently available PCH SKUs. Table above shows feature differences between the PCH SKUs. If a feature is not listed in the table it is considered a Base feature that is included in all SKUs The PCH provides hardware support for AHCI functionality when enabled by appropriate system configurations and software drivers.
Page 52: Mobile Intel
Anti-Theft NOTES: Contact your local Intel Field Sales Representative for currently available PCH SKUs Table above shows feature difference between the PCH SKUs. If a feature is not listed in the table it is considered a Base feature that is included in all SKUs The PCH provides hardware support for AHCI functionality when enabled by appropriate system configurations and software drivers.
Page 53: Signal Description
Signal Description Signal Description This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level.
Page 54: Pch Interface Signals Block Diagram (Not All Signals Are On All Skus)
Signal Description Figure 2-1. PCH Interface Signals Block Diagram (not all signals are on all SKUs) ® Intel Flexible AD[31:0] FDI_RX[P,N][7:4] Display FDI_RX[P,N[[3:0] C/BE[3:0]# FDI_FSYNC[0:1];FDI_LSYNC[0:1];FDI_INIT DEVSEL# Interface FRAME# IRDY# TRDY# Controller CL_CLK1 ; CL_DATA1 STOP# CL_RST1# Link PERR# PCI Express*...
Page 55: Direct Media Interface (Dmi) To Host Controller
Signal Description Direct Media Interface (DMI) to Host Controller Table 2-1. Direct Media Interface Signals Name Type Description DMI0TXP, Direct Media Interface Differential Transmit Pair 0 DMI0TXN DMI0RXP, Direct Media Interface Differential Receive Pair 0 DMI0RXN DMI1TXP, Direct Media Interface Differential Transmit Pair 1 DMI1TXN DMI1RXP, Direct Media Interface Differential Receive Pair 1...
Page 56: Pci Interface
Signal Description Table 2-2. PCI Express* Signals (Sheet 2 of 2) Name Type Description PERp6, PERn6 PCI Express Differential Receive Pair 6 PETp7, PETn7 PCI Express Differential Transmit Pair 7 PERp7, PERn7 PCI Express Differential Receive Pair 7 PETp8, PETn8 PCI Express Differential Transmit Pair 8 PERp8, PERn8 PCI Express Differential Receive Pair 8...
Page 57 Signal Description Table 2-3. PCI Interface Signals (Sheet 2 of 2) Name Type Description PCI Grants: GNT functionality is Reserved. GNT0# (not GNT[3:1]# pins can instead be used as GPIO. available in Pull-up resistors are not required on these signals. If pull-ups are mobile) used, they should be tied to the Vcc3_3 power rail.
Page 58: Serial Ata Interface
Signal Description Serial ATA Interface Table 2-4. Serial ATA Interface Signals (Sheet 1 of 3) Name Type Description Serial ATA 0 Differential Transmit Pairs: These are outbound high-speed differential signals to Port 0. SATA0TXP In compatible mode, SATA Port 0 is the primary master of SATA SATA0TXN Controller 1.
Page 59 Signal Description Table 2-4. Serial ATA Interface Signals (Sheet 2 of 3) Name Type Description Serial ATA 3 Differential Receive Pair: These are inbound high- speed differential signals from Port 3. In compatible mode, SATA Port 3 is the secondary slave of SATA SATA3RXP Controller 1 SATA3RXN...
Page 60 Signal Description Table 2-4. Serial ATA Interface Signals (Sheet 3 of 3) Name Type Description Serial ATA 3 General Purpose: Same function as SATA0GP, except for SATA Port 3. SATA3GP / GPIO37 If interlock switches are not required, this pin can be configured as GPIO37.
Page 61: Lpc Interface
Signal Description LPC Interface Table 2-5. LPC Interface Signals Name Type Description LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull- LAD[3:0] ups are provided. LFRAME# LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to LDRQ0#, request DMA or bus master access.
Page 62: Usb Interface
Signal Description USB Interface Table 2-7. USB Interface Signals (Sheet 1 of 2) Name Type Description Universal Serial Bus Port [1:0] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 USBP0P, and 1. These ports can be routed to EHCI Controller 1. USBP0N, USBP1P, NOTE: No external resistors are required on these signals.
Page 63: Power Management Interface
Description ACPRESENT: This input pin indicates when the platform is ® plugged into AC power or not. In addition to the previous Intel to EC communication, the PCH uses this information to implement ACPRESENT the Deep S4/S5 policies. For example, the platform may be...
Page 64 Signal Description Table 2-8. Power Management Interface Signals (Sheet 2 of 4) Name Type Description DRAM Power OK: This signal should connect to the processor’s SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAMPWROK OD O DRAM power is stable. This pin requires an external pull-up LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected to LAN_DISABLE_N on the PHY.
Page 65 PHY device. SLP_LAN# will always be deasserted in S0 and anytime SLP_A# is deasserted. SLP_LAN# behavior in Sx/Moff can be configured by Intel ME FW. When SLP_LAN#/GPIO Select Soft-strap is set to SLP_LAN#...
Page 66 Reset type: RSMRST# This signal is multiplexed with GPIO30 and SUSPWRDNACK. SUSPWRDNACK: Active high. Asserted by the PCH on behalf of the Intel ME when it does not require the PCH Suspend well to be SUSPWRDNACK / powered. SUSWARN# / Platforms are not expected to use this signal when the PCH’s Deep...
Page 67: Processor Interface
Signal Description Processor Interface Table 2-9. Processor Interface Signals Name Type Description Keyboard Controller Reset Processor: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the PCH’s other sources of INIT#. When the PCH detects the RCIN# assertion of this signal, INIT# is generated using a VLW message to the processor.
Page 68: System Management Interface
Signal Description 2.11 System Management Interface Table 2-11. System Management Interface Signals Name Type Description Intruder Detect: This signal can be set to disable the system if box INTRUDER# detected open. This signal’s status is readable, so it can be used like a GPI if the Intruder Detection is not needed.
Page 69: Miscellaneous Signals
Signal Description 2.13 Miscellaneous Signals Table 2-13. Miscellaneous Signals Name Type Description Internal Voltage Regulator Enable: This signal enables the internal 1.05 V regulators when pulled high. INTVRMEN This signal must be always pulled-up to VccRTC on desktop platforms and may optionally be pulled low on mobile platforms if using an external VR for the DcpSus rail.
Page 70: Intel
Intel High Definition Audio Serial Data In [3:0]: Serial TDM data inputs from the codecs. The serial input is single-pumped for a bit rate of 24 Mb/s for Intel High Definition Audio. These signals have integrated pull-down resistors, which are always HDA_SDIN[3:0] enabled.
Page 71: Controller Link
Signal Description 2.15 Controller Link Table 2-15. Controller Link Signals Signal Name Type Description CL_RST1# Controller Link Reset: Reserved. CL_CLK1 Controller Link Clock: Reserved. CL_DATA1 Controller Link Data: Reserved. 2.16 Serial Peripheral Interface (SPI) Table 2-16. Serial Peripheral Interface (SPI) Signals Name Type Description...
Page 72: Testability Signals
Signal Description 2.18 Testability Signals Table 2-18. Testability Signals Name Type Description Test Clock Input (TCK): The test clock input provides the clock JTAG_TCK for the JTAG test logic. Test Mode Select (TMS): The signal is decoded by the Test JTAG_TMS Access Port (TAP) controller to control test operations.
Page 73 Signal Description Table 2-19. Clock Interface Signals (Sheet 2 of 3) Name Type Description CLKOUT_PCIE[7:0] 100 MHz PCIe Gen2 specification differential output to PCI CLKOUT_PCIE[7:0] Express devices CLKIN_GND0_P, CLKIN_GND0_N Requires external pull-down termination (can be shared (Desktop Only) between P and N signals of the differential pair). CLKIN_GND1_P, CLKIN_GND1_N PCIECLKRQ0# /...
Page 74: Lvds Signals
NOTE: It is highly recommended to prioritize 27/14.318/24/48 MHz clocks on CLKOUTFLEX1 and CLKOUTFLEX3 outputs. Intel does not recommend configuring the 27/14.318/24/48 MHz clocks on CLKOUTFLEX0 and CLKOUTFLEX2 if more than 2x 33 MHz clocks in addition to the Feedback clock are used on the CLKOUT_PCI outputs.
Page 75: Analog Display /Vga Dac Signals
Signal Description Table 2-20. LVDS Interface Signals (Sheet 2 of 2) Name Type Description LVDS Panel Power Enable: Panel power control enable control for LVDS or embedded DisplayPort*. L_VDD_EN (available in Desktop) This signal is also called VDD_DBL in the CPIS specification and is used to control the VDC source to the panel logic.
Page 76: Intel
Signal Description ® ® 2.22 Intel Flexible Display Interface (Intel FDI) ® Table 2-22. Intel Flexible Display Interface Signals Signal Name Type Description FDI_RXP[3:0] Display Link 1 positive data in FDI_RXN[3:0] Display Link 1 negative data in FDI_FSYNC[0] Display Link 1 Frame sync...
Page 77: Digital Display Signals
Signal Description 2.23 Digital Display Signals Table 2-23. Digital Display Interface Signals (Sheet 1 of 3) Name Type Description Port B: Capable of SDVO / HDMI / DVI / DisplayPort SDVO DDPB_[0]P: red DDPB_[1]P: green DDPB_[2]P: blue DDPB_[3]P: clock HDMI / DVI Port B Data and Clock Lines DDPB_[3:0]P DDPB_[0]P: TMDSB_DATA2 DDPB_[1]P: TMDSB_DATA1...
Page 78 Signal Description Table 2-23. Digital Display Interface Signals (Sheet 2 of 3) Name Type Description SDVO_CTRLDATA Port B: HDMI Control Data. Shared with Port B SDVO SDVO_INTP SDVO_INTP: Serial Digital Video Input Interrupt SDVO_INTN SDVO_INTN: Serial Digital Video Input Interrupt Complement. SDVO_TVCLKINP: Serial Digital Video TVOUT Synchronization SDVO_TVCLKINP Clock.
Page 79 Signal Description Table 2-23. Digital Display Interface Signals (Sheet 3 of 3) Name Type Description Port D: Capable of HDMI / DVI / DP HDMI / DVI Port D Data and Clock Lines DDPD_[0]P: TMDSC_DATA2 DDPD_[1]P: TMDSC_DATA1 DDPD_[2]P: TMDSC_DATA0 DDPD_[3:0]P DDPD_[3]P: TMDSC_CLK DisplayPort Port D DDPD_[0]P: Display Port Lane 0...
Page 80: General Purpose I/O Signals
Signal Description 2.24 General Purpose I/O Signals Notes: 1. GPIO Configuration registers within the Core Well are reset whenever PWROK is deasserted. 2. GPIO Configuration registers within the Suspend Well are reset when RSMRST# is asserted, CF9h reset (06h or 0Eh), or SYS_RESET# is asserted. However, CF9h reset and SYS_RESET# events can be masked from resetting the Suspend well GPIO by programming appropriate GPIO Reset Select (GPIO_RST_SEL) registers.
Page 81 Signal Description Table 2-24. General Purpose I/O Signals (Sheet 2 of 4) Power Blink Name Type Tolerance Default Description Well Capability Desktop: Multiplexed with REQ3#. GPIO54 5.0 V Core Native (Note 11) Mobile: Used as GPIO only Desktop: Multiplexed with GNT2# GPIO53 3.3 V Core...
Page 82 GPIO25 Mobile: Multiplexed with 3.3 V Suspend Native (Mobile Only) PCIECLKRQ3# Desktop: Can be used as PROC_MISSING configured using Intel ME firmware. Mobile: Unmultiplexed GPIO24 3.3 V Suspend NOTE: GPIO24 configuration register bits are not cleared by CF9h reset event.
Page 83 When this signal is configured as GPO the output stage is an open drain. ® In an Intel ME disabled system, GPIO31 may be used as ACPRESENT from the EC. GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as a GPIO (when configured as an output) by BIOS.
Page 84: Manageability Signals
Signal Description 2.25 Manageability Signals The following signals can be optionally used by Intel Management Engine supported applications and appropriately configured by Intel Management Engine firmware. When configured and used as a manageability function, the associated host GPIO functionality is no longer available. If the manageability function is not used in a platform, the signal can be used as a host General Purpose I/O or a native function.
Page 85: Power And Ground Signals
1.05 V supply for the Active Sleep Well. Provides power to the Intel ME and VccASW integrated LAN. This plane must be on in S0 and other times the Intel ME or integrated LAN is used. Power supply for DMI.
Page 86 Signal Description Table 2-26. Power and Ground Signals (Sheet 2 of 2) Name Description 1.8 V or 3.3 V supply for DF_TVS. This pin should be pulled up to 1.8 V or VccDFTERM 3.3 V core. 1.05 V supply for Display PLL A Analog Power. This power is supplied by the VccADPLLA core well.
Page 87: Pin Straps
PCH and processor very early in the boot process before BIOS or SW intervention. When Descriptor Mode is enabled, the PCH will read Soft Strap data out of the SPI device prior to the deassertion of reset to both the Intel Management Engine and the Host system. Please refer to Section 5.24.2...
Page 88 Boot BIOS Destination Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will not ® affect SPI accesses initiated by Intel or Integrated GbE LAN. PCI Boot BIOS destination is not supported on Mobile Datasheet...
Page 89 ME Debug Mode after PLTRST# deasserts. Asserting the HDA_SDO high on the ® rising edge of PWROK will also halt Intel Management Engine after chipset bring up and disable runtime Intel ME features. This is a debug mode and must not be asserted after manufacturing/debug.
Page 90 1.8 V from VccVRM when Voltage Select sampled low. Low = Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High = Intel ME Crypto TLS cipher suite with confidentiality This signal has a weak internal pull-down. NOTES: Rising edge of...
Page 91: External Rtc Circuitry
Signal Description Table 2-27. Functional Strap Definitions (Sheet 5 of 5) When Signal Usage Comment Sampled This signal has a weak internal pull-down. NOTES: Rising edge of The internal pull-down is disabled after SATA2GP/GPIO36 Reserved PWROK PLTRST# deasserts. This signal should not be pulled high when strap is sampled.
Page 92 Signal Description Datasheet...
Page 93: Pch Pin States
PCH Pin States PCH Pin States Integrated Pull-Ups and Pull-Downs Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2) Signal Resistor Type Nominal Notes Pull-up/Pull- CL_CLK1 32/100 13, 21 down Pull-up/Pull- CL_DATA1 32/100 13, 21 down CLKOUTFLEX[3:0]/GPIO[67:64] Pull-down 1, 16 GPIO15 Pull-down...
Page 94 PCH Pin States Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2) Signal Resistor Type Nominal Notes SATA[3:2]GP/GPIO[37:36] Pull-down 3, 15 ACPRESENT/GPIO31 Pull-down PCIECLKRQ5#/GPIO44 Pull-up 1, 20 PCIECLKRQ7#/GPIO46 Pull-up 1, 20 SATA1GP/GPIO19 Pull-up SUSACK# Pull-up PECI Pull-down 0.35k NOTES: Simulation data shows that these resistor values can range from 10 k...
Page 95: Output And I/O Signals Planes And States
PCH Pin States Output and I/O Signals Planes and States Table 3.2 Table 3-3 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used: “High-Z”...
Page 96 PCH Pin States Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 2 of 6) Power During Immediately Signal Name S0/S1 S4/S5 Plane Reset after Reset FRAME# Core High-Z High-Z High-Z GNT0#, GNT[3:1]#7/ Core High High High...
Page 97 PCH Pin States Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 3 of 6) Power During Immediately Signal Name S0/S1 S4/S5 Plane Reset after Reset Power Management LAN_PHY_PWR_CTRL Suspend Defined Defined Defined GPIO12 PLTRST# Suspend High...
Page 98 Running CLKOUTFLEX[3:0]/ Core Running Running GPIO[67:64] XTAL25_OUT Core Running Running Running XCLK_RCOMP Core High-Z High-Z High-Z ® Intel High Definition Audio Interface HDA_RST# Suspend Defined HDA_SDO Suspend Defined HDA_SYNC Suspend Defined HDA_BCLK Suspend UnMultiplexed GPIO Signals GPIO8 Suspend High High...
Page 99 VGA_HSYNC Core VGA_VSYNC Core VGA_DDC_CLK Core High-Z High-Z High-Z VGA_DDC_DATA Core High-Z High-Z High-Z VGA_IRTN Core High-Z High-Z High-Z ® Intel Flexible Display Interface FDI_FSYNC[1:0] Core High-Z High-Z High-Z FDI_LSYNC[1:0] Core High-Z High-Z High-Z FDI_INT Core High-Z High-Z High-Z Datasheet...
Page 100 PETp/n[8:1] low until port is enabled by software. The SLP_A# state will be determined by Intel ME Policies. The state of signals in S3-5 will be defined by Intel ME Policies. This signal is sampled as a functional strap during reset. Refer to Functional straps definition table for usage.
Page 101: Power Plane And States For Output And I/O Signals For Mobile Configurations
PCH Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 1 of 6) Power During Immediately Signal Name S0/S1 S4/S5 Plane Reset after Reset states PCI Express* PET[8:1]p, PET[8:1]n Core Defined Defined DMI[3:0]TXP, Core Defined...
Page 102 PCH Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 2 of 6) Power During Immediately Signal Name S0/S1 S4/S5 Plane Reset after Reset states Power Management CLKRUN# Core Defined Defined PLTRST# Suspend High High...
Page 103 Running Running Running Running CLKOUT_PCIE[7:0] N CLKOUT_PCI[4:0] Core Running Running Running Running CLKOUTFLEX[3:0]/ Running/ Core Running Running GPIO[67:64] ® Intel High Definition Audio Interface HDA_RST# Suspend Defined Defined HDA_SDO Suspend HDA_SYNC Suspend HDA_BCLK Suspend HDA_DOCK_EN#/ Core High High High High...
Page 104 PCH Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 4 of 6) Power During Immediately Signal Name S0/S1 S4/S5 Plane Reset after Reset states UnMultiplexed GPIO Signals GPIO8 Suspend High High Defined Defined Defined...
Page 105 CRT_DDC_CLK Core High-Z High-Z High-Z High-Z CRT_DDC_DATA Core High-Z High-Z High-Z High-Z CRT_IRTN Core High-Z High-Z High-Z High-Z ® Intel Flexible Display Interface FDI_FSYNC[1:0] Core High-Z High-Z Defined Defined FDI_LSYNC[1:0] Core High-Z High-Z Defined Defined FDI_INT Core High-Z High-Z Defined...
Page 106 Finger-Print Sensor device. When soft strap is not enabled, signal defaults to GP Input. Based on Intel ME wake events and Intel ME state. SUSPWRDNACK is the default mode of operation. If system supports Deep S4/S5, subsequent boots will default to SUSWARN# Pins are tri-stated prior to APWROK assertion During Reset.
Page 107: Power Planes For Input Signals
PCH Pin States Pin-state indicates SUSPWRDNACK in Non-Deep S4/S5, Deep S4/S5 after RTC power failure. Pin-state indicates SUSWARN# in Deep S4/S5 supported platforms. When Controller Reset Bit of Global Control Register (D27:F0 Offset HDBAR 08h Bit 0) gets set, this pin will start toggling. Not all signals or pin functionalities may be available on a given SKU.
Page 108 PCH Pin States Table 3-4. Power Plane for Input Signals for Desktop Configurations (Sheet 2 of 3) Signal Name Power Well Driver During Reset S0/S1 S4/S5 SATA Interface SATA[5:0]RXP, Core SATA Drive Driven SATA[5:0]RXN SATAICOMPI Core High-Z Driven External Device or External SATA4GP/GPIO16 Core Driven...
Page 109 SDVO controller device Driven SDVO_INTN SDVO_TVCLKINP, Core SDVO controller device Driven SDVO_TVCLKINN SDVO_STALLP, Core SDVO controller device Driven SDVO_STALLN ® Intel Flexible Display Interface FDI_RXP[7:0], Core Processor Driven FDI_RXN[7:0] Clock Interface CLKIN_SATA_N, Core External pull-down CLKIN_SATA_P CLKIN_DOT_96P, Core External pull-down...
Page 110: Power Plane For Input Signals For Mobile Configurations
PCH Pin States Table 3-5. Power Plane for Input Signals for Mobile Configurations (Sheet 1 of 3) Signal Name Power Well Driver During Reset S0/S1 S4/S5 states DMI[3:0]RXP, Core Processor Driven Driven DMI[3:0]RXN PCI Express* PER[8:1]p, PER[8:1]n Core PCI Express* Device Driven Driven LPC Interface...
Page 111 RTCRST# External RC Circuit High High High High SRTCRST# External RC Circuit High High High High ® Intel High Definition Audio Interface ® Intel High Definition HDA_SDIN[3:0] Suspend Driven Audio Codec SPI Interface SPI_MISO Internal Pull-up Driven Driven Driven...
Page 112 PEG_B_CLKRQ#/ GPIO56 XTAL25_IN Core Clock Generator High-Z High-Z REFCLK14IN Core External pull-down CLKIN_PCILOOPBACK Core Clock Generator High-Z High-Z ® Intel Flexible Display Interface FDI_RXP[7:0], Core Processor Driven Driven FDI_RXN[7:0] Digital Display Interface DDP[B:C:D]_HPD Core External Pull-down Driven Driven SDVO_INTP, Core...
Page 113: Pch And System Clocks
PCH and System Clocks PCH and System Clocks PCH provides a complete system clocking solution through Integrated Clocking. PCH based platforms require several single-ended and differential clocks to synchronize signal operation and data propagation system-wide between interfaces, and across clock domains. In Integrated Clock mode, all the system clocks will be provided by PCH from a 25 MHz crystal generated clock input.
Page 114: Clock Outputs
PCH and System Clocks Table 4-2. Clock Outputs Spread Clock Domain Frequency Usage Spectrum Single Ended 33 MHz outputs to PCI connectors/ devices. One of these signals must be connected to CLKIN_PCILOOPBACK to function as a PCI clock loopback. This allows skew control for CLKOUT_PCI[4:0] 33 MHz variable lengths of CLKOUT_PCI[4:0].
Page 115: Functional Blocks
FDI logic and link clocks and below states. Source clock is from XCK_PLL. PCIEPXP_PLL drives clocks 2.5 GHz/625 MHz/ ® to PCIe ports and Intel ME engine (in S0 state). Can be 500 MHz/250 MHz/125 MHz optionally used to supply DMI clocks.
Page 116: Clock Configuration Access Overview
Modulators and other clock configuration registers will be handled by the Intel ME engine. The parameters to be loaded will reside in the Intel ME data region of the SPI Flash device. BIOS would only have access to the register set through a set of Intel MEI commands to the Intel ME.
Page 117: Functional Description
Functional Description Functional Description This chapter describes the functions and interfaces of the PCH. DMI-to-PCI Bridge (D30:F0) The DMI-to-PCI bridge resides in PCI Device 30, Function 0 on Bus 0. This portion of the PCH implements the buffering and control logic between PCI and Direct Media Interface (DMI).
Page 118: Pci Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7)
Functional Description PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) There are eight root ports available in the PCH. The root ports are compliant to the PCI Express 2.0 specification running at 5.0 GT/s. The ports all reside in Device 28, and take Function 0 –...
Page 119: Power Management
Functional Description 5.2.2 Power Management 5.2.2.1 S3/S4/S5 Support Software initiates the transition to S3/S4/S5 by performing an I/O write to the Power Management Control register in the PCH. After the I/O write completion has been returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction Layer Packet) message on its downstream link.
Page 120: Serr# Generation
Functional Description 5.2.2.4 SMI/SCI Generation Interrupts for power management events are not supported on legacy operating systems. To support power management on non-PCI Express aware operating systems, PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set. When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/ F5/F6/F7:Offset DCh:Bit 31) to be set.
Page 121: Presence Detection
Functional Description 5.2.4.1 Presence Detection When a module is plugged in and power is supplied, the physical layer will detect the presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/ F5:Offset 5Ah:Bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:Bit 3). If SLCTL.PDE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3/ F4/F5/F6/F7:Offset 58h:Bit 5) are both set, the root port will also generate an interrupt.
Page 122: Gigabit Ethernet Controller (B0:D25:F0)
Gigabit Ethernet Controller (B0:D25:F0) The PCH integrates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is ® compatible with the Intel 82579 Platform LAN Connect device. The integrated GbE controller provides two interfaces for 10/100/1000 Mb/s and manageability operation: •...
Page 123 Functional Description The integrated GbE controller provides a system interface using a PCI Express function. A full memory-mapped or I/O-mapped interface is provided to the software, along with DMA mechanisms for high performance data transfer. The integrated GbE controller features are: •...
Page 124: Gbe Pci Express* Bus Interface
Functional Description 5.3.1 GbE PCI Express* Bus Interface The GbE controller has a PCI Express interface to the host processor and host memory. The following sections detail the bus transactions. 5.3.1.1 Transaction Layer The upper layer of the host architecture is the transaction layer. The transaction layer connects to the device core using an implementation specific protocol.
Page 125: Completion With Unsuccessful Completion Status
Functional Description 5.3.2.2 Completion with Unsuccessful Completion Status A completion with unsuccessful completion status (any status other than 000) is dropped and not processed by the integrated GbE controller. Furthermore, the request that corresponds to the unsuccessful completion is not retried. When this unsuccessful completion status is received, the System Error bit in the PCI configuration space is set.
Page 126: Wake Up
Functional Description 5.3.4.1 Wake Up The integrated GbE controller supports two types of wake-up mechanisms: 1. Advanced Power Management (APM) Wake Up 2. ACPI Power Management Wake Up Both mechanisms use an internal logic signal to wake the system up. The wake-up steps are as follows: 1.
Page 127: Configurable Leds
Functional Description 5.3.4.1.2 ACPI Power Management Wake Up The integrated GbE controller supports ACPI Power Management based Wake ups. It can generate system wake-up events from three sources: • Receiving a Magic Packet. • Receiving a Network Wake Up Packet. •...
Page 128: Function Level Reset Support (Flr)
Function Level Reset Support (FLR) The integrated GbE controller supports FLR capability. FLR capability can be used in ® conjunction with Intel Virtualization Technology. FLR allows an operating system in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform.
Page 129: Lpc Bridge (With System And Management Functions) (D31:F0)
Functional Description 5.3.6.1.3 FLR Completion The Initiate FLR bit is reset (cleared) when the FLR reset completes. This bit can be used to indicate to the software that the FLR reset completed. Note: From the time the Initiate FLR bit is written to 1b, software must wait at least 100 ms before accessing the function.
Page 130: Lpc Cycle Types
Functional Description 5.4.1.1 LPC Cycle Types The PCH implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.1. Table 5-7 shows the cycle types supported by the PCH. Table 5-7. LPC Cycle Types Supported Cycle Type Comment Memory Read...
Page 131: Cycle Type / Direction (Cyctype + Dir)
Functional Description 5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR) The PCH always drives Bit 0 of this field to 0. Peripherals running bus master cycles must also drive Bit 0 to 0. Table 5-9 shows the valid bit encodings. Table 5-9.
Page 132: Sync
Functional Description 5.4.1.5 SYNC Valid values for the SYNC field are shown in Table 5-11. Table 5-11. SYNC Bit Definition Bits[3:0] Indication Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA 0000 request deassertion and no more transfers desired for that channel. Short Wait: Part indicating wait-states.
Page 133: Bus Master Cycles
Functional Description 5.4.1.9 I/O Cycles For I/O cycles targeting registers specified in the PCH’s decode ranges, the PCH performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the PCH breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses.
Page 134: Dma Operation (D31:F0)
Functional Description DMA Operation (D31:F0) The PCH supports LPC DMA using the PCH’s DMA controller. The DMA controller has registers that are fixed in the lower 64 KB of I/O space. The DMA controller is configured using registers in the PCI configuration space. These registers allow configuration of the channels for use by LPC DMA.
Page 135: Address Compatibility Mode
Functional Description 5.5.1.2 Rotating Priority Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7). Channels 0–3 rotate as a group of 4. They are always placed between Channel 5 and Channel 7 in the priority list.
Page 136: Autoinitialize
Functional Description The address shifting is shown in Table 5-13. Table 5-13. Address Shifting in 16-Bit I/O DMA Transfers 16-Bit I/O Programmed Output 8-Bit I/O Programmed Address (Ch 5–7) Address Address (Ch 0–3) (Shifted) A[16:1] A[16:1] A[15:0] A[23:17] A[23:17] A[23:17] NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
Page 137: Lpc Dma
Functional Description LPC DMA DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0–3 are 8-bit channels. Channels 5–7 are 16-bit channels.
Page 138: General Flow Of Dma Transfers
Functional Description In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the PCH, there is no assurance that the cycle has not been granted and will shortly run on LPC.
Page 139: Dma Request Deassertion
Functional Description 5.6.6 DMA Request Deassertion An end of transfer is communicated to the PCH through a special SYNC field transmitted by the peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting LDREQ#. If a DMA transfer is several bytes (such as, a transfer from a demand mode device) the PCH needs to know when to deassert the DMA request based on the data currently being transferred.
Page 140: 8254 Timers (D31:F0)
Functional Description Under default operation, the host only performs 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. The method by which this communication between host and peripheral through system BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are motherboard devices, no “plug-n-play”...
Page 141: Timer Programming
Functional Description 5.7.1 Timer Programming The counter/timers are programmed in the following fashion: 1. Write a control word to select a counter. 2. Write an initial count for that counter. 3. Load the least and/or most significant bytes (as required by Control Word Bits 5, 4) of the 16-bit counter.
Page 142: Reading From The Interval Timer
Functional Description 5.7.2 Reading from the Interval Timer It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods for reading the counters: a simple read operation, counter Latch command, and the Read-Back command. Each is explained below. With the simple read and counter latch command methods, the count must be read according to the programmed format;...
Page 143: 8259 Interrupt Controllers (Pic) (D31:F0)
Functional Description Both count and status of the selected counters may be latched simultaneously. This is functionally the same as issuing two consecutive, separate Read Back commands. If multiple count and/or status Read Back commands are issued to the same counters without any intervening reads, all but the first are ignored.
Page 144: Interrupt Handling
Functional Description Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and IRQ13. Note: Active-low interrupt sources (such as, the PIRQ#s) are inverted inside the PCH. In the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred.
Page 145: Initialization Command Words (Icwx)
Functional Description 5.8.1.3 Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to the processor if an asserted interrupt is not masked. 3.
Page 146: Operation Command Words (Ocw)
The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, Bit 0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based system. 5.8.3 Operation Command Words (OCW) These command words reprogram the Interrupt controller to operate in various interrupt modes.
Page 147: Special Fully-Nested Mode
Functional Description 5.8.4.2 Special Fully-Nested Mode This mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode is programmed to the master controller. This mode is similar to the fully-nested mode with the following exceptions: •...
Page 148: Automatic End Of Interrupt Mode
Functional Description 5.8.4.6 Cascade Mode The PIC in the PCH has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This configuration can handle up to 15 separate priority levels. The master controls the slaves through a three bit internal bus. In the PCH, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector.
Page 149: Masking Interrupts
Functional Description 5.8.5 Masking Interrupts 5.8.5.1 Masking on an Individual Interrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking IRQ2 on the master controller masks all requests for service from the slave controller.
Page 150: Advanced Programmable Interrupt Controller (Apic) (D31:F0)
Functional Description Advanced Programmable Interrupt Controller (APIC) (D31:F0) In addition to the standard ISA-compatible PIC described in the previous chapter, the PCH incorporates the APIC. While the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in either a uni-processor or multi- processor system.
Page 151: Pci / Pci Express* Message-Based Interrupts
5.9.4 IOxAPIC Address Remapping ® To support Intel Virtualization Technology, interrupt messages are required to go through similar address remapping as any other memory request. Address remapping allows for domain isolation for interrupts, so a device assigned in one domain is not allowed to generate an interrupt to another domain.
Page 152: Serial Interrupt (D31:F0)
Functional Description 5.10 Serial Interrupt (D31:F0) The PCH supports a serial IRQ scheme. This allows a single signal to be used to report interrupt requests. The signal used to transmit this information is shared between the host, the PCH, and all peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is used by all PCI signals.
Page 153: Data Frames
Functional Description 5.10.2 Data Frames Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1 clock each: •...
Page 154: Data Frame Format
Functional Description 5.10.5 Data Frame Format Table 5-20 shows the format of the data frames. For the PCI interrupts (A–D), the output from the PCH is AND’d with the PCI input signal. This way, the interrupt can be signaled using both the PCI interrupt input signal and using the SERIRQ signal (they are shared).
Page 155: Real Time Clock (D31:F0)
Functional Description 5.11 Real Time Clock (D31:F0) The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose usage. Three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 µs to 500 ms, and end of update cycle notification.
Page 156: Interrupts
Functional Description 5.11.2 Interrupts The real-time clock interrupt is internally routed within the PCH both to the I/O APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the PCH, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored. However, the High Performance Event Timers can also be mapped to IRQ8#;...
Page 157: Configuration Bits Reset By Rtcrst# Assertion
Functional Description Table 5-21. Configuration Bits Reset by RTCRST# Assertion Default Bit Name Register Location Bit(s) State Alarm Interrupt Register B (General I/O space (RTC Index Enable (AIE) Configuration) (RTC_REGB) + 0Bh) Register C (Flag Register) I/O space (RTC Index Alarm Flag (AF) (RTC_REGC) + 0Ch)
Page 158: Processor Interface (D31:F0)
Functional Description 5.12 Processor Interface (D31:F0) The PCH interfaces to the processor with following pin-based signals other than DMI: • Standard Outputs to processor: PROCPWRGD, PMSYNCH, PECI • Standard Input from processor: THRMTRIP# Most PCH outputs to the processor use standard buffers. The PCH has separate V_PROC_IO signals that are pulled up at the system level to the processor voltage, and thus determines VOH for the outputs to the processor.
Page 159: Init (Initialization)
Functional Description 5.12.1.2 INIT (Initialization) The INIT# VLW Message is asserted based on any one of several events described in Table 5-22. When any of these events occur, INIT# is asserted for 16 PCI clocks, then driven high. Note: INIT3_3V# is functionally identical to INIT# VLW but it is a physical signal at 3.3 V on desktop SKUs only.
Page 160: Dual-Processor Issues
Functional Description 5.12.1.4 NMI (Non-Maskable Interrupt) Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-23. Table 5-23. NMI Sources Cause of NMI Comment SERR# goes active (either internally, Can instead be routed to generate an SCI, through externally using SERR# signal, or using the NMI2SCI_EN bit (Device 31:Function 0, TCO message from processor)
Page 161: Power Management
— ACPI G2/S5 state – Soft Off (SOFF) — Power Failure Detection and Recovery — Deep S4/S5 • Intel Management Engine Power Management Support — Wake events from the Intel Management Engine (enabled from all S-States including Catastrophic S5 conditions) 5.13.2 PCH and System Power States Table 5-24 shows the power states defined for PCH-based platforms.
Page 162: State Transition Rules For The Pch
Functional Description Table 5-24. General Power States for Systems Using the PCH (Sheet 2 of 2) State/ Legacy Name / Description Substates Soft Off (SOFF): System context is not maintained. All power is shut off except G2/S5 for the logic required to restart. A full boot is required when waking. Soft Off (SOFF): System context is not maintained.
Page 163: System Power Planes
SLP_A# the Intel Management Engine power planes, LAN subsystem power, and the SPI flash power. This signal is asserted in Sx/Moff when both host and Intel ME SLP_LAN# WOL are not supported. This signal can be use to control power to the Intel GbE PHY.
Page 164: Causes Of Smi And Sci
Functional Description In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not (see Section 13.1.3).
Page 165: Pci Express* Sci
PERIODIC_EN=1 PERIODIC_STS 64 ms timer expires SWSMI_TMR_EN=1 SWSMI_TMR_STS Enhanced USB Legacy Support Event LEGACY_USB2_EN = 1 LEGACY_USB2_STS Enhanced USB Intel Specific Event INTEL_USB2_EN = 1 INTEL_USB2_STS Serial IRQ SMI reported none SERIRQ_SMI_STS Device monitors match address in its none DEVTRAP_STS...
Page 166: C-States
Functional Description 5.13.5 C-States PCH-based systems implement C-states by having the processor control the states. The chipset exchanges messages with the processor as part of the C-state flow, but the chipset does not directly control any of the processor impacts of C-states, such as voltage levels or processor clocking.
Page 167: Sleep States
Functional Description 5.13.6.4 Conditions for Re-Starting the PCI Clock • A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started. • When the PCH observes the CLKRUN# signal asserted for 1 (free running) clock, the PCH deasserts the STP_PCI# signal to the clock synthesizer within 4 (free running) clocks.
Page 168: Exiting Sleep States
Functional Description Table 5-28. Sleep Types Sleep Type Comment System lowers the processor’s power consumption. No snooping is possible in this state. The PCH asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is only retained to devices needed to wake from this sleeping state, as well as to the memory.
Page 169 Reset Types include: Power Button override, Intel ME initiated power button override, Intel ME initiated host partition reset with power down, Intel ME Watchdog Timer, SMBus unconditional power down, processor thermal trip, PCH catastrophic temperature event.
Page 170: Pci Express* Wake# Signal And Pme Event Message
Functional Description It is important to understand that the various GPIs have different levels of functionality when used as wake events. The GPIs that reside in the core power well can only generate wake events from sleep states where the core well is powered. Also, only certain GPIs are “ACPI Compliant,”...
Page 171: Deep S4/S5
A combination of conditions is required for entry into Deep S4/S5. All of the following must be met: — Intel ME in Moff — AND either A or B as defined below: a. ((DPS4_EN_AC AND S4) OR (DPS5_EN_AC AND S5)) (desktop only) b.
Page 172: Event Input Signals And Their Usage
Note that ACPRESENT has some behaviors that are different from the other Deep S4/ S5 wake events. If the Intel ME has enabled ACPRESENT as a wake event then it behaves just like any other Intel ME Deep S4/S5 wake event. However, even if...
Page 173: Transitions Due To Power Button
Functional Description Table 5-34. Transitions Due to Power Button Present Event Transition/Action Comment State SMI or SCI generated (depending on SCI_EN, Software typically initiates a S0/Cx PWRBTN# goes low PWRBTN_EN and Sleep state GLB_SMI_EN) Wake Event. Transitions to S1–S5 PWRBTN# goes low Standard wakeup S0 state No effect since no power...
Page 174: Ri# (Ring Indicator)
Functional Description 5.13.8.2 RI# (Ring Indicator) The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states. Table 5-35 shows when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the PCH generates an interrupt based on RI# active, and the interrupt will be set up as a Break event.
Page 175: Alt Access Mode
Functional Description The PCH provides filtering for short low glitches on the THRMTRIP# signal in order to prevent erroneous system shut downs from noise. Glitches shorter than 25nsec are ignored. During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, and PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry, power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PCH PWROK = 0, or SYS_PWROK = 0.
Page 176: Write Only Registers With Read Paths In Alt Access Mode
Functional Description 5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode The registers described in Table 5-36 have read paths in ALT access mode. The access number field in the table indicates which register will be returned per access to that port.
Page 177 Functional Description Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2) Restore Data Restore Data # of # of Access Data Access Data Addr Addr DMA Chan 6 base count low DMA Chan 0–3 Command byte DMA Chan 6 base count DMA Chan 0–3 Request...
Page 178: 10System Power Supplies, Planes, And Signals
Functional Description 5.13.9.2 PIC Reserved Bits Many bits within the PIC are reserved, and must have certain values written in order for the PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. When reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-37.
Page 179: 11Clock Generators
SLP_A# output signal can be used to cut power to the Intel Management Engine, Clock chip and SPI flash on a platform that support the M3 state. SLP_LAN# output signal can be used to cut power to the external Intel 82579 GbE PHY device.
Page 180: 1Apm Power Management (Desktop Only)
Functional Description However, the operating system is assumed to be at least APM enabled. Without APM calls, there is no quick way to know when the system is idle between keystrokes. The PCH does not support burst modes. 5.13.12.1 APM Power Management (Desktop Only) The PCH has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable register, generates an SMI once per minute.
Page 181: Causes Of Host And Global Resets
® Intel Management Engine Triggered Host Reset No (Note 1) without power cycle Intel Management Engine Triggered Host Reset with No (Note 1) power cycle Intel Management Engine Triggered Global Reset Intel Management Engine Initiated Host Reset with Yes (Note 3)
Page 182: System Management (D31:F0)
Functional Description 5.14 System Management (D31:F0) The PCH provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. Features and functions can be augmented using external A/D converters and GPIO, as well as an external microcontroller.
Page 183: Tco Modes
In TCO Legacy/Compatible mode, only the host SMBus is utilized. The TCO Slave is connected to the host SMBus internally by default. In this mode, the Intel Management Engine SMBus controllers are not used and should be disabled by soft strap.
Page 184: Tco Legacy/Compatible Mode Smbus Configuration
Functional Description Figure 5-5. TCO Legacy/Compatible Mode SMBus Configuration TCO Legacy/Compatible Mode Intel ME SMBus Controller 3 Intel ME SMBus Controller 2 Intel ME SMBus Controller 1 PCI/PCIe* uCtrl (Slave) Device SMBus Host SMBus Legacy Sensors Party (Master or Slave...
Page 185: Advanced Tco Mode
SMBus controllers must be enabled by soft strap in the flash descriptor. SMLink0 is dedicated to integrated LAN use and when an Intel PHY 82579 is connected to SMLink0, a soft strap must be set to indicate that the PHY is connected to SMLink0.
Page 186: General Purpose I/O (D31:F0)
Functional Description 5.15 General Purpose I/O (D31:F0) The PCH contains up to 70 General Purpose Input/Output (GPIO) signals for Desktop PCH and 75 General Purpose Input/Output (GPIO) for Mobile PCH. Each GPIO can be configured as an input or output signal. The number of inputs and outputs varies depending on the configuration.
Page 187: Serial Post Codes Over Gpio
Functional Description Once these registers are locked down, they become Read-Only registers and any software writes to these registers will have no effect. To unlock the registers, the GPIO Lockdown Enable (GLE) bit is required to be cleared to ‘0’. When the GLE bit changes from a ‘1’...
Page 188: Serial Message Format
Functional Description the on/off state of the LED. To allow flexibility in pull-up resistor values for power optimization, the frequency of the transmission is programmable using the DRS field in the GP_GB_CMDSTS register. The serial bit stream is Manchester encoded. This choice of transmission ensures that a transition will be seen on every clock.
Page 189: Sata Host Controller (D31:F2, F5)
Functional Description The idle field is enforced by the hardware and is at least 2 bit times long. The hardware will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in hardware prevents time-based counting in BIOS as the hardware is immediately ready for the next serial code when the Go bit is cleared.
Page 190: Sata Feature Support
Functional Description 5.16.1 SATA 6 Gb/s Support The PCH supports SATA 6 Gb/s transfers with all capable SATA devices. SATA 6 Gb/s support is available on PCH Ports 0 and 1 only. Note: PCH ports 0 and 1 also support SATA 1.5 Gb/s and 3.0 Gb/s device transfers. 5.16.2 SATA Feature Support Feature...
Page 191: Theory Of Operation
Functional Description 5.16.3 Theory of Operation 5.16.3.1 Standard ATA Emulation The PCH contains a set of registers that shadow the contents of the legacy IDE registers. The behavior of the Command and Control Block registers, PIO, and DMA data transfers, resets, and interrupts are all emulated. Note: The PCH will assert INTR when the master device completes the EDD command regardless of the command completion status of the slave device.
Page 192: Function Level Reset Support (Flr)
The SATA Host Controller supports the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel Virtualization Technology. FLR allows an operating system in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform.
Page 193: Power Management Operation
Functional Description By using the PCH’s built-in Intel Rapid Storage Technology, there is no loss of PCI resources (request/grant pair) or add-in card slot. ® Intel Rapid Storage Technology functionality requires the following items: ® 1. The PCH SKU enabled for Intel Rapid Storage Technology 2.
Page 194: Power State Transitions
Functional Description Finally, SATA defines three PHY layer power states, which have no equivalent mappings to parallel ATA. They are: • PHY READY – PHY logic and PLL are both on and active • Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer than 10 ns •...
Page 195: Sata Device Presence
Functional Description 5.16.8.2.4 Non-AHCI Mode PME# Generation When in non-AHCI mode (legacy mode) of operation, the SATA controller does not generate PME#. This includes attach events (since the port must be disabled), or interlock switch events (using the SATAGP pins). 5.16.8.3 SMI Trapping (APM) Device 31:Function2:Offset C0h (see...
Page 196: 10Sata Led
Functional Description 5.16.10 SATA LED The SATALED# output is driven whenever the BSY bit is set in any SATA port. The SATALED# is an active-low open-drain output. When SATALED# is low, the LED should be active. When SATALED# is high, the LED should be inactive. 5.16.11 AHCI Operation The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a...
Page 197: 2Message Format
Functional Description to the actual bit stream transmission. The Host will drive SLOAD low for at least 5 SCLOCK then only start the bit stream by driving the SLOAD to high. SLOAD will be driven high for 1 SCLOCK follow by vendor specific pattern that is default to “0000” if software has yet to program the value.
Page 198: 3Led Message Type
Functional Description The SAF-TE, SES-2, and SGPIO message formats are defined in the corresponding specifications, respectively. The LED message type is defined in Section 5.16.12.3. It is the responsibility of software to ensure the content of the message format is correct. If the message type is not programmed as 'LED' for this controller, the controller shall not take any action to update its LEDs.
Page 199: 4Sgpio Waveform
Functional Description 5.16.12.4 SGPIO Waveform Figure 5-9. Serial Data transmitted over the SGPIO Interface Datasheet...
Page 200: 13External Sata
The PCH supports external SATA. External SATA utilizes the SATA interface outside of the system box. The usage model for this feature must comply with the Serial ATA II Cables and Connectors Volume 2 Gold specification at www.sata-io.org. Intel validates two configurations: 1.
Page 201: Interrupt Mapping
Functional Description 5.17.2 Interrupt Mapping Mapping Option #1 (Legacy Replacement Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the mapping found in Table 5-42. Table 5-42. Legacy Replacement Routing Timer 8259 Mapping APIC Mapping Comment In this case, the 8254 timer will IRQ0...
Page 202: Enabling The Timers
Functional Description Periodic Mode Timer 0 is the only timer that supports periodic mode. Refer to Section 2.3.9.2.2 of the IA-PC HPET Specification for a description of this mode. The following usage model is expected: 1. Software clears the ENABLE_CNF bit to prevent any interrupts. 2.
Page 203: Handling Interrupts
Functional Description 5.17.6 Handling Interrupts If each timer has a unique interrupt and the timer has been configured for edge- triggered mode, then there are no specific steps required. No read is required to process the interrupt. If a timer has been configured to level-triggered mode, then its interrupt must be cleared by the software.
Page 204: Usb Ehci Host Controllers (D29:F0 And D26:F0)
5.18.1.1 BIOS Initialization BIOS performs a number of platform customization steps after the core well has powered up. Contact your Intel Field Representative for additional PCH BIOS information. 5.18.1.2 Driver Initialization See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0.
Page 205: Usb 2.0 Enhanced Host Controller Dma
Functional Description 5.18.3 USB 2.0 Enhanced Host Controller DMA The PCH USB 2.0 EHC implements three sources of USB packets. They are, in order of priority on USB during each microframe: 1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port), 2.
Page 206: Usb 2.0 Power Management
Functional Description 5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following actions are taken when this occurs: • The Host System Error status bit is set. •...
Page 207: Usb 2.0 Legacy Keyboard Operation
Functional Description 5.18.7.4 ACPI System States The EHC behavior as it relates to other power management states in the system is summarized in the following list: • The System is always in the S0 state when the EHC is in the D0 state. However, when the EHC is in the D3 state, the system may be in any power management state (including S0).
Page 208: Theory Of Operation
Functional Description 5.18.9.1 Theory of Operation There are two operational modes for the USB debug port: 1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host controller driver. In Mode 1, the Debug Port controller is required to generate a “keepalive”...
Page 209 Functional Description 5.18.9.1.1 OUT Transactions An Out transaction sends data to the debug device. It can occur only when the following are true: • The debug port is enabled • The debug software sets the GO_CNT bit • The WRITE_READ#_CNT bit is set The sequence of the transaction is: 1.
Page 210 Functional Description 5.18.9.1.2 IN Transactions An IN transaction receives data from the debug device. It can occur only when the following are true: • The debug port is enabled • The debug software sets the GO_CNT bit • The WRITE_READ#_CNT bit is reset The sequence of the transaction is: 1.
Page 211 Functional Description 5.18.9.1.3 Debug Software Enabling the Debug Port There are two mutually exclusive conditions that debug software must address as part of its startup processing: • The EHCI has been initialized by system software • The EHCI has not been initialized by system software Debug software can determine the current ‘initialized’...
Page 212: 10Ehci Caching
Typically in the presence of periodic devices with multiple millisecond poll periods, the periodic schedule will be idle for several frames between polls. The Intel USB Pre-Fetch Based Pause feature is disabled by setting bit 4 of EHCI Configuration Register Section 16.2.1.
Page 213: 13Usb Overcurrent Protection
Functional Description 5.18.12.1.3 FLR Completion The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be used to indicate to the software that the FLR reset is completed. Note: From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before accessing the function.
Page 214: Integrated Usb 2.0 Rate Matching Hub
Functional Description 5.19 Integrated USB 2.0 Rate Matching Hub 5.19.1 Overview The PCH has integrated two USB 2.0 Rate Matching Hubs (RMH). One hub is connected to each of the EHCI controllers as shown in Figure 5-10. The Hubs convert low and full- speed traffic into high-speed traffic.
Page 215: Smbus Controller (D31:F3)
Functional Description 5.20 SMBus Controller (D31:F3) The PCH provides an System Management Bus (SMBus) 2.0 host controller as well as an SMBus Slave Interface. The host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The PCH is also capable of operating in a mode in which it can communicate with I C compatible devices.
Page 216: Command Protocols
Functional Description The PCH supports the System Management Bus (SMBus) Specification, Version 2.0. Slave functionality, including the Host Notify protocol, is available on the SMBus pins. The SMLink and SMBus signals can be tied together externally depending on TCO mode used.
Page 217 Functional Description Process Call The process call is so named because a command sends data and waits for the slave to return a value dependent on that data. The protocol is simply a Write Word followed by a Read Word, but without a second command or stop condition. When programmed for the Process Call command, the PCH transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers.
Page 218: C Block Read
Functional Description C Read This command allows the PCH to perform block reads to certain I C devices, such as serial E PROMs. The SMBus Block Read supports the 7-bit addressing mode only. However, this does not allow access to devices using the I C “Combined Format”...
Page 219: Bus Arbitration
Functional Description Block Write–Block Read Process Call The block write-block read process call is a two-part message. The call begins with a slave address and a write condition. After the command code the host issues a write byte count (M) that describes how many more bytes will be written in the first part of the message.
Page 220: Bus Timing
Functional Description 5.20.3 Bus Timing 5.20.3.1 Clock Stretching Some devices may not be able to handle their clock toggling at the rate that the PCH as an SMBus master would like. They have the capability of stretching the low time of the clock.
Page 221: Smbalert
Functional Description Table 5-46. Enables for SMBus Slave Write and SMBus Host Events SMB_SMI_EN (Host INTREN (Host Configuration Register, Event Control I/O Register, Event D31:F3:Offset 40h, Offset 02h, Bit 0) Bit 1) Wake generated when asleep. Slave Write to Wake/ Slave SMI# generated when SMI# Command awake (SMBUS_SMI_STS).
Page 222: Smbus Slave Interface
Functional Description 5.20.7 SMBus Slave Interface The PCH SMBus Slave interface is accessed using the SMBus. The SMBus slave logic will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting Protocol device. The slave interface allows the PCH to decode cycles, and allows an external microcontroller to perform specific actions.
Page 223: Slave Write Registers
Functional Description Table 5-48. Slave Write Registers Register Function Command Register. See Table 5-49 for legal values written to this register. 1–3 Reserved Data Message Byte 0 Data Message Byte 1 6–7 Reserved Reserved 9–FFh Reserved NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor.
Page 224: Format Of Read Command
Functional Description Table 5-49. Command Types (Sheet 2 of 2) Command Description Type Reserved SMLINK_SLV_SMI. When the PCH detects this command type while in the S0 state, it sets the SMLINK_SLV_SMI_STS bit (see Section 13.9.5). This command should only be used if the system is in an S0 state. If the message is received during S1–S5 states, the PCH acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set.
Page 225: Data Values For Slave Read Registers
Functional Description Table 5-51. Data Values for Slave Read Registers (Sheet 1 of 2) Register Bits Description Reserved for capabilities indication. Should always return 00h. Future chips may return another value to indicate different capabilities. System Power State 000 = S0 001 = S1 010 = Reserved 011 = S3 100 = S4 101 = S5 110 = Reserved 111 = Reserved Reserved Reserved...
Page 226: Slave Read Of Rtc Time Bytes
Functional Description Table 5-51. Data Values for Slave Read Registers (Sheet 2 of 2) Register Bits Description Contents of the Message 1 register. Refer to Section 13.9.8 for the description of this register. Contents of the Message 2 register. Refer to Section 13.9.8 for the description of this register.
Page 227: Format Of Host Notify Command
Functional Description For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the external SMBus master reads the hour as 11, then proceeds to read the minute, it is possible that the rollover happens between the reads and the minute is read as 0. This results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes.
Page 228: Thermal Management
Functional Description 5.21 Thermal Management 5.21.1 Thermal Sensor The PCH incorporates one on-die Digital thermal sensor (DTS) for thermal management. The thermal sensor can provide PCH temperature information to an EC or SIO device that can be used to determine how to control the fans. This thermal sensor is located near the DMI interface.
Page 229: Thermal Reporting Over System Management Link 1 Interface (Smlink1)
Functional Description 5.21.1.1.1 Recommended Programming for Available Trip Points There may be a ±2 °C offset due to thermal gradient between the hot-spot and the location of the thermal sensor. Trip points should be programmed to account for this temperature offset between the hot-spot T and the thermal sensor.
Page 230: Supported Addresses
PCH has been programmed, it will start responding to a request while the system is in S0 or S1. To implement this thermal reporting capability, the platform is required to have appropriate Intel ME firmware, BIOS support, and compatible devices that support the SMBus protocol. 5.21.2.1...
Page 231: Ime
C Write Commands to the Intel Table 5-53 lists the write commands supported by the Intel ME. All bits in the write commands must be written to the PCH or the operation will be aborted. For example, for 6-bytes write commands, all 48 bits must be written or the operation will be aborted.
Page 232: Block Read Command - Byte Definition
Functional Description Table 5-54. Block Read Command – Byte Definition Byte Definition Processor Package temperature, in absolute degrees Celsius (C). This is not relative to some max or limit, but is the maximum in absolute degrees. Byte 0 If the processor temperature collection has errors, this field will be FFh. Read value represents bits [7:0] of PTV (Processor Temperature Value) The PCH temp in degrees C.
Page 233: Read Data Format
Functional Description 5.21.2.4 Read Data Format For each of the data fields an ERROR Code is listed below. This code indicates that the PCH failed in its access to the device. This would be for the case where the read returned no data, or some illegal value.
Page 234 ® ® and the Intel ME can process this change. If the Intel ME is already in the process of collecting data and doing the compares, then it will continue to use the old limits during this round of compares, and then use the new limits in the next compare window.
Page 235: Bios Set Up
The only long delay where there can be a NACK is if the internal Intel ME engine is reset. This is due to some extreme error condition and is therefore rare. In this case the NACK may occur for up to 30 seconds.
Page 236: Case For Considerations
Functional Description 5.21.2.9 Case for Considerations Below are some corner cases and some possible actions that the external controller could take. Note that a 1-byte sequence number is available to the data read by the external controller. Each time the PCH updates the thermal information it will increment the sequence number.
Page 237 Functional Description external controller sees a NACK from the PCH, then it should restart its sequence counter, or otherwise be aware that the NACK condition needs to be factored into the sequence number usage. The use of sequence numbers is not required, but is provided as a means to ensure correct PCH FW operation.
Page 238: High Definition Audio Overview (D27:F0)
The PCH High Definition Audio (HDA) controller communicates with the external codec(s) over the Intel High Definition Audio serial link. The controller consists of a set of DMA engines that are used to move samples of digitally encoded data between system memory and an external codec(s).
Page 239: Exiting D3/Crst# When Docked
In this case the HD Audio Bus Driver is called directly by this interrupt instead of being notified by the plug-N-play IRP. 10. Intel HD Audio Bus Driver software “discovers” the dock codecs by comparing the bits now set in the STATESTS register with the bits that were set prior to the docking event.
Page 240: Cold Boot/Resume From S3 When Docked
Functional Description 5.22.1.3 Cold Boot/Resume from S3 When Docked 1. When booting and resuming from S3, PLTRST# switches from asserted to deasserted. This clears the DCKCTL.DA bit and the dock state machines. Because the dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN# deasserted) and DOCK_RST# is asserted.
Page 241: Surprise Undock
Functional Description 5.22.1.6 Surprise Undock 1. In the surprise undock case the user undocks before software has had the opportunity to gracefully halt the stream to the dock codec and initiate the hardware undock sequence. 2. A signal on the docking connector is connected to the switch that isolates the dock codec signals from the PCH HD Audio link signals (DOCK_DET# in the conceptual diagram).
Page 242: Serial Peripheral Interface (Spi)
ME Firmware 7.0 Intel ME is a platform-level solution that utilizes multiple system components including: • The Intel ME is the general purpose controller that resides in the PCH. It operates in parallel to and is resource-isolated from the host processor.
Page 243 Descriptor Mode is required for all SKUs of the PCH. It enables many new features of the chipset: • Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software • Intel Active Management Technology • Intel Management Engine Firmware • PCI Express* root port configuration •...
Page 244: Region Size Versus Erase Granularity Of Flash Components
ME and BIOS regions. The ME region will contain ® firmware to support Intel Advanced Fan Speed Control, Intel Active Management Technology, and ASF 2.0. Table 5-55. Region Size versus Erase Granularity of Flash Components Size with 4 KB...
Page 245: Flash Descriptor Sections
Functional Description Figure 5-11. Flash Descriptor Sections OEM Section Descriptor Upper MAP Management Engine VSCC Table Reserved PCH Soft Straps Master Region Component Descriptor Signature 10 h 1. The Flash signature selects Descriptor Mode as well as verifies if the flash is programmed and functioning.
Page 246: Region Access Control Table
Intel ME can always Management Read / Write read from and write to Read / Write Engine Intel ME Region GbE software can Gigabit Ethernet Read / Write Read / Write always read from and write to GbE region Platform Data...
Page 247 A variety of serial flash devices exist in the market. For a serial flash device to be compatible with the PCH SPI bus, it must meet the minimum requirements detailed in the following sections. Note: All PCH platforms have require Intel Management engine Firmware. Datasheet...
Page 248 • Flash part must be uniform 4-KB erasable block throughout the entire device or have 64 KB blocks with the first block (lowest address) divided into 4-KB or 8-KB blocks. • Write protection scheme must meet SPI flash unlocking requirements for Intel ME. Datasheet...
Page 249: Hardware Sequencing Commands And Opcode Requirements
0h to indicate that the flash is unlocked. If bits [5:2] return a non zero values, the Intel ME firmware will send a write of 00h to the status register. This must keep the flash part unlocked.
Page 250 ‘increment’ the bits within a page that have been designated as the counter. The Intel ME firmware usage model requires the capability for multiple data updates within any given page. These data updates occur using byte-writes without executing a preceding erase to the given page.
Page 251: Flash Protection Mechanism Summary
The PCH-based platform must have a SPI flash connected directly to the PCH with a valid descriptor and Intel Management Engine Firmware. BIOS may be stored in other locations such as Firmware Hub and SPI flash hooked up directly to an embedded controller for Mobile platforms.
Page 252: Recommended Pinout For 8-Pin Serial Flash Device
Functional Description 5.24.7 SPI Flash Device Recommended Pinout Table 5-59 contains the recommended serial flash device pin-out for an 8-pin device. Use of the recommended pin-out on an 8-pin device reduces complexities involved with designing the serial flash device onto a motherboard and allows for support of a common footprint usage model (refer to Section 5.24.8.1).
Page 253 Functional Description The common footprint usage model is desirable during system debug and by flash content developers since the leadless device can be easily removed and reprogrammed without damage to device leads. When the board and flash content is mature for high- volume production, both the socketed leadless solution and the soldered down leaded solution are available through BOM selection.
Page 254: Analog Port Characteristics
Functional Description 5.26 PCH Display Interfaces The PCH integrates one Analog, LVDS (mobile only) and three Digital Ports B, C, and D. Each Digital Port can transmit data according to one or more protocols. Digital Port B, C, and D can be configured to drive natively HDMI, DisplayPort, or DVI. Digital Port B also supports Serial Digital Video Out (SDVO) that converts one protocol to another.
Page 255 Functional Description 5.26.1.1 Integrated RAMDAC The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that transforms the digital data from the graphics and video subsystems to analog data for the VGA monitor. The PCH’s integrated 340.4 MHz RAMDAC supports resolutions up to 2048x1536 at 75 Hz.
Page 256: Lvds Signals And Swing Voltage
Functional Description Figure 5-13. LVDS Signals and Swing Voltage Logic values of 1s and 0s are represented by the differential voltage between the pair of signals. As shown in the Figure 5-14 a serial pattern of 1100011 represents one cycle of the clock. Figure 5-14.
Page 257: Panel Power Sequencing
Functional Description 5.26.2.1.2 Single Channel versus Dual Channel Mode In the single channel mode, only Channel-A is used. Channel-B cannot be used for single channel mode. In the dual channel mode, both Channel-A and Channel-B pins are used concurrently to drive one LVDS display. In Single Channel mode, Channel A can take 18 bits of RGB pixel data, plus 3 bits of timing control (HSYNC/VSYNC/DE) and output them on three differential data pair outputs;...
Page 258: Hdmi Overview
Functional Description 5.26.2.1.4 LVDS DDC The display pipe selected by the LVDS display port is programmed with the panel timing parameters that are determined by installed panel specifications or read from an onboard EDID ROM. The programmed timing values are then ‘locked’ into the registers to prevent unwanted corruption of the values.
Page 259: Dp Overview
Functional Description 5.26.2.3 Digital Video Interface (DVI) The PCH Digital Ports can be configured to drive DVI-D. DVI uses TMDS for transmitting data from the transmitter to the receiver which is similar to the HDMI protocol but the audio and CEC. Refer to the HDMI section for more information on the signals and data transmission.
Page 260: Pch Supported Audio Formats Over Hdmi And Displayport
Functional Description 5.26.2.5 Embedded DisplayPort Embedded DisplayPort (eDP*) is a embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PCs. eDP is supported only on Digital Port D. Like DisplayPort, Embedded DisplayPort also consists of a Main Link, Auxiliary channel, and a optional Hot Plug Detect signal.
Page 261: Sdvo Conceptual Block Diagram
Functional Description Figure 5-18. SDVO Conceptual Block Diagram TV Clock in Stall Interrupt Control Clock Party LVDS SDVO Control Data Panel External Device RED B GREEN B BLUE B 5.26.2.9.1 Control Bus Communication to SDVO registers and if utilized, ADD2 PROMs and monitor DDCs, are accomplished by using the SDVOCTRLDATA and SDVOCTRLCLK signals through the SDVO device.
Page 262: Pch Digital Port Pin Mapping
Functional Description 5.26.3 Mapping of Digital Display Interface Signals Table 5-60. PCH Digital Port Pin Mapping Port DisplayPort* PCH Display HDMI* Signals SDVO Signals Description Signals Port Pin details DPB_LANE3 TMDSB_CLK SDVOB_CLK DDPB_[3]P DPB_LANE3# TMDSB_CLKB SDVOB_CLK# DDPB_[3]N DPB_LANE2 TMDSB_DATA0 SDVOB_BLUE DDPB_[2]P DPB_LANE2# TMDSB_DATA0B...
Page 263: Display Co-Existence Table
, C, E , C, E , C, E , C, E ® • A = Single Pipe Single Display, Intel Dual Display Clone (Only 24-bpp), or Extended Desktop Mode • C = Clone Mode • E = Extended Desktop Mode •...
Page 264 PCH. The display data from the frame buffer is processed in the display engine of the processor and sent to the PCH over the Intel FDI where it is transcoded as per the display protocol and driven to the display monitor.
Page 265: Virtualization Support For High Precision Event Timer (Hpet)
5.27.3 Support for Function Level Reset (FLR) in PCH Intel VT-d allows system software (VMM/OS) to assign I/O devices to multiple domains. The system software, then, requires ways to reset I/O devices or their functions within, as it assigns/re-assigns I/O devices from one domain to another. The reset capability is required to ensure the devices have undergone proper re-initialization and are not keeping the stale state.
Page 266 Functional Description § § Datasheet...
Page 267 Ballout Definition Ballout Definition This chapter contains the PCH Ballout information. Desktop PCH Ballout This section contains the Desktop PCH ballout. Figure 6-1, Figure 6-2, Figure 6-3, and Figure 6-4 show the ballout from a top of the package quadrant view. Table 6-1 is the BGA ball list, sorted alphabetically by signal name.
Page 268: Desktop Pch Ballout (Top View - Upper Left)
Ballout Definition Figure 6-1. Desktop PCH Ballout (Top View - Upper Left) CRT_DDC CRT_BLU VSS_NCTF VSS_NCTF V5REF VccADAC _DATA CLKOUTF GNT3# / CRT_VSY CRT_GRE XCLK_RC VSS_NCTF AD14 AD21 C/BE2# AD24 LEX3 / VssADAC GPIO55 GPIO67 CRT_DDC PERR# AD13 DAC_IREF _CLK PIRQH# / CRT_HSY VSS_NCTF...
Page 269: Desktop Pch Ballout (Top View - Lower Left)
Ballout Definition Figure 6-2. Desktop PCH Ballout (Top View - Lower Left) USBP8P USBP5N USBP5P VccSus3_3 VccASW VccASW USBP4P USBP11P USBP11N USBP7N USBP7P VccSus3_3 USBP3P USBP4N VccSus3_3 VccASW VccCore VccCore VccCore USBP3N USBP2N USBP6N USBP6P USBP1N USBP1P VccSus3_3 VccASW VccCore VccCore VccCore VccSus3_3...
Page 270: Desktop Pch Ballout (Top View - Upper Right)
Ballout Definition Figure 6-3. Desktop PCH Ballout (Top View - Upper Right) CLKOUT_ VccADPLL DDPB_HP DDPD_HP VSS_NCT VSS_NCT VccVRM PCIE7P CLKOUT_ CLKOUT_ VccADPLL CLKOUT_ SDVO_INT DDPC_HP VSS_NCT VccVRM DDPC_0P DDPC_1P DDPC_3N PCIE5P PCIE7N PCIE6P XTAL25_I CLKOUT_ CLKOUT_ SDVO_ST SDVO_INT DDPB_3N DDPC_0N DDPC_2P PCIE5N...
Page 271: Desktop Pch Ballout (Top View - Lower Right)
Ballout Definition Figure 6-4. Desktop PCH Ballout (Top View - Lower Right) TP33 TP29 VccCore VccCore VccIO VccIO VccSus3_ CLKOUT_ CLKOUT_ DMI_ZCO DMI_IRCO VccIO TP25 TP21 DMI_P DMI_N DMI2RBIA VccCore VccCore VccCore VccCore DcpSus VccIO CLKIN_D CLKIN_D VccIO DMI0RXN DMI0RXP MI_P MI_N VccCore...
Page 272: Desktop Pch Ballout By Signal Name
Ballout Definition Table 6-1. Desktop PCH Ballout By Signal Name Desktop PCH Ball Desktop PCH Ball Ball # Ball # Desktop PCH Ball Ball # CLKIN_DMI_N CLKOUTFLEX1 / GPIO65 CLKIN_DMI_P A20GATE BB57 CLKOUTFLEX2 / CLKIN_DOT_96N BD38 BF15 GPIO66 CLKIN_DOT_96P BF38 BF17 CLKOUTFLEX3 / GPIO67...
Page 273 Ballout Definition Desktop PCH Ball Desktop PCH Ball Desktop PCH Ball Ball # Ball # Ball # DDPC_CTRLDATA AL14 FDI_RXN3 IRDY# BF11 DDPC_HPD FDI_RXN4 JTAG_TCK BA43 DDPD_0N FDI_RXN5 JTAG_TDI BC52 DDPD_0P FDI_RXN6 JTAG_TDO BF47 DDPD_1N FDI_RXN7 JTAG_TMS BC50 DDPD_1P FDI_RXP0 L_BKLTCTL AG12 DDPD_2N...
Page 274 Ballout Definition Desktop PCH Ball Desktop PCH Ball Desktop PCH Ball Ball # Ball # Ball # OC0# / GPIO59 BM43 PETp5 SATA2RXP AL49 OC1# / GPIO40 BD41 PETp6 SATA2TXN AL56 OC2# / GPIO41 BG41 PETp7 SATA2TXP AL53 OC3# / GPIO42 BK43 PETp8 SATA3COMPI...
Page 275 Ballout Definition Desktop PCH Ball Desktop PCH Ball Desktop PCH Ball Ball # Ball # Ball # SMBDATA BR49 TP13 AE49 USBP10P BJ25 SML0ALERT# / TP14 AE41 USBP11N BJ31 BU49 GPIO60 TP15 AE43 USBP11P BK31 SML0CLK BT51 TP16 AE50 USBP12N BF27 SML0DATA BM50...
Page 276 Ballout Definition Desktop PCH Ball Desktop PCH Ball Desktop PCH Ball Ball # Ball # Ball # VccASW AN28 VccIO AJ38 AE56 VccASW AR24 VccIO BR36 VccASW AR26 VccIO VccASW AR28 VccIO AY22 VccASW AR30 VccIO AE40 VccIO BA38 VccASW AR36 VccIO AG38...
Page 277 Ballout Definition Desktop PCH Ball Desktop PCH Ball Desktop PCH Ball Ball # Ball # Ball # AG30 AT18 BF41 AG36 AT43 BF43 AG43 AT47 BF46 AG44 AT52 BF52 AG46 BG22 AG50 AU24 BG25 AG53 AU26 BG27 AH52 AU28 BG31 BG33 AJ22 AV12...
Page 278 Ballout Definition Desktop PCH Ball Desktop PCH Ball Desktop PCH Ball Ball # Ball # Ball # AL43 AL44 VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF BM57 VSS_NCTF VSS_NCTF BP57 VSS_NCTF VSS_NCTF VSS_NCTF BU52 VSS_NCTF BU54 VSS_NCTF VSS_NCTF VSS_NCTF VssADAC WAKE# BC44 XCLK_RCOMP XTAL25_IN XTAL25_OUT...
Page 279 Ballout Definition Mobile PCH Ballout This section contains the PCH ballout. Figure 6-5, Figure 6-6, Figure 6-7 Figure 6-8 show the ballout from a top of the package quadrant view. Table 6-2is the BGA ball list, sorted alphabetically by signal name. Datasheet...
Page 280: Mobile Pch Ballout (Top View - Upper Left)
Ballout Definition Figure 6-5. Mobile PCH Ballout (Top View - Upper Left) Vss_NCTF Vss_NCTF Vss_NCTF DDPD_3N PERp7 PERn6 PERp3 PERp1 TP28 CLKIN_GND Vss_NCTF DDPD_HPD PERp5 Vcc3_3 Vss_NCTF TP24 DDPD_3P PERn7 PERp6 PERn5 PERn3 PERn1 TP32 CLKIN_GND Vss_NCTF VccADPLLB DDPD_1N DDPD_2N PERn4 PERp2 TP31...
Page 281: Mobile Pch Ballout (Top View - Lower Left)
Ballout Definition Figure 6-6. Mobile PCH Ballout (Top View - Lower Left) LVD_VREFH LVD_VREFL VccAClk VccASW VccASW VccASW VccASW VccASW VccASW CLKOUT_PC CLKOUT_PC TP19 TP20 CLKOUT_PE CLKOUT_PE CLKOUT_PE CLKOUT_PE VccClkDMI IE1N IE1P G_B_N G_B_P G_A_P G_A_N CLKOUT_PC CLKOUT_PC VccASW VccASW VccASW VccASW IE2N...
Page 282: Mobile Pch Ballout (Top View - Upper Right)
Ballout Definition Figure 6-7. Mobile PCH Ballout (Top View - Upper Right) DMI_ZCOM VccAPLLEX DMI3RXP DMI2RXP FDI_RXN0 FDI_RXN5 FDI_RXP6 V_PROC_IO Vss_NCTF Vss_NCTF Vss_NCTF VccAPLLD DMI2RBIAS FDI_RXN3 FDI_RXP7 Vss_NCTF DMI_IRCOM VccAFDIPL DMI3RXN DMI2RXN FDI_RXP0 FDI_RXP3 FDI_RXP5 FDI_RXN6 FDI_RXN7 Reserved Vss_NCTF CLKIN_DMI FDI_RXP2 Reserved Reserved...
Page 283: Mobile Pch Ballout (Top View - Lower Right)
Ballout Definition Figure 6-8. Mobile PCH Ballout (Top View - Lower Right) VccCore VccCore VccIO SATA2RXN SATA2RXP SATA4TXN SATA4TXP VccCore VccIO VccIO SATA3COM SATA3RCO SATA3RXP SATA3RXN SATA5TXN SATA5TXP VccASW VccCore VccASW VccASW Vcc3_3 SATAICOM SATAICOM SPI_CS0# TP16 SATA4RXN SATA4RXP SATA5RXN SATA5RXP VccASW VccASW...
Page 284: Mobile Pch Ballout By Signal Name
Ballout Definition Table 6-2. Mobile PCH Ballout By Signal Name Mobile PCH Ball Mobile PCH Ball Ball # Ball # Name Name Mobile PCH Ball Ball # Name CLKOUT_PCIE6P DDPC_1N AY43 CLKOUT_PCIE7N DDPC_1P AY45 A20GATE CLKOUT_PCIE7P DDPC_2N BA47 ACPRESENT / GPIO31 CLKOUT_PEG_A_N AB37...
Page 285 Ballout Definition Mobile PCH Ball Mobile PCH Ball Mobile PCH Ball Ball # Ball # Ball # Name Name Name DRAMPWROK HDA_SDIN2 TS_VSS1 DSWVRMEN HDA_SDIN3 TS_VSS2 AK11 FDI_FSYNC0 AV12 HDA_SDO TS_VSS3 AH10 FDI_FSYNC1 BC10 HDA_SYNC TS_VSS4 AK10 FDI_INT AW16 INIT3_3V# NC_1 FDI_LSYNC0 AV14...
Page 286 Ballout Definition Mobile PCH Ball Mobile PCH Ball Mobile PCH Ball Ball # Ball # Ball # Name Name Name PCIECLKRQ1# / PETp7 BB40 SATA3RXP AB10 GPIO18 PETp8 AY38 SATA3TXN PCIECLKRQ2# / PIRQA# SATA3TXP GPIO20 PIRQB# SATA4GP / GPIO16 PCIECLKRQ3# / GPIO25 PIRQC# SATA4RXN...
Page 287 Ballout Definition Mobile PCH Ball Mobile PCH Ball Mobile PCH Ball Ball # Ball # Ball # Name Name Name SML1CLK / GPIO58 TP20 AB45 USBP12P SML1DATA / GPIO75 TP21 USBP13N SPI_CLK TP22 USBP13P SPI_CS0# TP23 AY16 USBRBIAS SPI_CS1# TP24 BG46 USBRBIAS# SPI_MISO...
Page 288 Ballout Definition Mobile PCH Ball Mobile PCH Ball Mobile PCH Ball Ball # Ball # Ball # Name Name Name VccASW VccIO AN17 AA34 VccASW VccIO AN21 AB11 VccASW VccIO AN26 AB14 VccIO AN27 AB39 VccClkDMI AB36 VccIO AP21 VccCore AA23 VccIO AP23...
Page 289 Ballout Definition Mobile PCH Ball Mobile PCH Ball Mobile PCH Ball Ball # Ball # Ball # Name Name Name AF26 AL48 AV38 AF27 AM11 AF29 AM14 AV43 AF31 AM36 AF38 AM39 AW14 AM43 AW18 AF42 AM45 AF46 AM46 AW22 AW26 AW28 AN29...
Page 290 Ballout Definition Mobile PCH Ball Mobile PCH Ball Mobile PCH Ball Ball # Ball # Ball # Name Name Name BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BE10 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BF30 BF38 BF40...
Page 291 Ballout Definition Mobile PCH Ball Mobile PCH Ball Ball # Ball # Name Name Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF VssADAC VssALVDS AK37 WAKE# XCLK_RCOMP XTAL25_IN XTAL25_OUT § § BE16 BC16 BG28 BJ28 Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF BD49 Vss_NCTF...
Page 292 Ballout Definition Datasheet...
Page 293 Package Information Package Information Desktop PCH package • FCBGA package • Package size: 27 mm x 27 mm • Ball Count: 942 • Ball pitch: 0.7 mm The Desktop PCH package information is shown in Figure 7-1. Note: All dimensions, unless otherwise specified, are in millimeters. Datasheet...
Page 294: Desktop Pch Package Drawing
Package Information Figure 7-1. Desktop PCH Package Drawing Datasheet...
Page 295 Package Information Mobile PCH Package • FCBGA package • Package size: 25 mm x 25 mm • Ball Count: 989 • Ball pitch: 0.6 mm The Mobile PCH package information is shown in Figure 7-2 Note: All dimensions, unless otherwise specified, are in millimeters. Datasheet...
Page 296: Mobile Pch Package Drawing
Package Information Figure 7-2. Mobile PCH Package Drawing § § Datasheet...
Page 297: Storage Conditions
ABSOLUTE STORAGE moisture barrier bags, or desiccant. Intel branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board attach storage temperature limits are not specified for non-Intel branded boards.
Page 298: Mobile Thermal Design Power
Electrical Characteristics Table 8-2. Mobile Thermal Design Power Thermal Design Power (TDP) Notes Standard 3.9 W 3.4 W Low Power 3.4 W Absolute Maximum Ratings Table 8-3. PCH Absolute Maximum Ratings Parameter Maximum Limits Voltage on any 5 V Tolerant Pin with respect to Ground (V5REF = 5 V) -0.5 to V5REF + 0.5 V Voltage on any 3.3 V Pin with respect to Ground -0.5 to Vcc3_3 + 0.4 V...
Page 299: Pch Power Supply Range
Electrical Characteristics PCH Power Supply Range Table 8-4. PCH Power Supply Range Power Supply Minimum Nominal Maximum 1.05 V 1.00 V 1.05 V 1.10 V 1.5 V 1.43 V 1.50 V 1.58 V 1.8 V 1.71 V 1.80 V 1.89 V 3.3 V 3.14 V 3.30 V...
Page 300: (Mobile Only)
Electrical Characteristics Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room temperature. Numbers based on a worst-case of 3 displays - 2 DisplayPort and 1 CRT, even though only 2 display pipes are enabled at any one time.
Page 301 Electrical Characteristics Table 8-6. Measured I (Mobile Only) (Sheet 2 of 2) S0 Iccmax S0 Iccmax S0 Idle S0 Idle Current Current Current Current Sx Idle Voltage Iccmax Voltage Rail Integrated External Integrated External Current Current Graphics Graphics Graphics Graphics VccVRM 0.167 0.127...
Page 302: Dc Characteristic Input Signal Association
Electrical Characteristics Table 8-7. DC Characteristic Input Signal Association (Sheet 1 of 2) Symbol Associated Signals PCI Signals (Desktop Only): AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, VIH1/VIL1 IRDY#, PAR, PERR#, PLOCK#, REQ[3:0]#, SERR#, STOP#, TRDY# Interrupt Signals: PIRQ[D:A]#, PIRQ[H:E]# (5V Tolerant) GPIO Signals: GPIO[54, 52, 50, 5:2] Digital Display Port Hot Plug Detect: DDPB_HPD, DDPC_HPD, DDPD_HPD VIH2/VIL2 Power Management Signals: PWRBTN#, RI#, SYS_RESET#, WAKE#,...
Page 303 Table 8-7. DC Characteristic Input Signal Association (Sheet 2 of 2) Symbol Associated Signals Intel High Definition Audio Signals: HDA_SDIN[3:0] (3.3V Mode) Strap Signals: HDA_SDO, HDA_SYNC (Strap purposes only) VIH11/VIL11 GPIO Signals: GPIO13 NOTE: See VIL_HDA/VIH_HDA for High Definition Audio Low Voltage Mode...
Page 304: Dc Input Characteristics
Electrical Characteristics Table 8-8. DC Input Characteristics (Sheet 1 of 3) Symbol Parameter Unit Notes VIL1 Input Low Voltage –0.5 0.3 × 3.3 V VIH1 Input High Voltage 0.5 × 3.3 V V5REF + 0.5 VIL2 Input Low Voltage — VIH2 Input High Voltage —...
Page 305 Electrical Characteristics Table 8-8. DC Input Characteristics (Sheet 2 of 3) Symbol Parameter Unit Notes VIL12 Input Low Voltage -0.3 — (Absolute Minimum) VIH12 Input High Voltage — 1.150 (Absolute Maximum) – VIL13 Input Low Voltage 0.78 VIH13 Input High Voltage VccRTC + 0.5 –...
Page 306 Electrical Characteristics Table 8-8. DC Input Characteristics (Sheet 3 of 3) Symbol Parameter Unit Notes Minimum Input Voltage -0.15 0.15 VIL_XTAL25 Maximum Input Voltage VIH_XTAL25 VIMIN17- Minimum Input Voltage - — mVdiffp-p Gen3i 6.0 Gb/s internal SATA VIMAX17- Maximum Input Voltage - —...
Page 307: Dc Characteristic Output Signal Association
Processor Signal: PMSYNCH, PROCPWRGD VOH1/VOL1 LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LFRAME#/FWH[4], INIT3_3V# Power Management Signal: LAN_PHY_PWR_CTRL ® Intel High Definition Audio Signals: HDA_DOCK_EN# (Mobile Only), HDA_DOCK_RST# (Mobile Only) PCI Signals: AD[31:0], C/BE[3:0], DEVSEL#, FRAME#, IRDY#, PAR, VOH2/VOL2 PCIRST#, GNT[3:0]#, PME#(1) Interrupt Signals: PIRQ[D:A], PIRQ[H:E]#(1)
Page 308 Associated Signals VHSOI VHSOH VHSOL USB Signals: USBP[13:0][P:N] in High-speed Mode VCHIRPJ VCHIRPK VOH_HDA/ ® Intel High Definition Audio Signals: HDA_RST#, HDA_SDO, HDA_SYNC VOL_HDA VOL_JTAG JTAG Signals: JTAG_TDO Single Ended Clock Interface Output Signals: CLKOUT_PCI[4:0], VOH_PCICLK/ CLKOUTFLEX[3:0] VOL_PCICLK GPIO Signals: [67:64]...
Page 309: Dc Output Characteristics
Electrical Characteristics Table 8-10. DC Output Characteristics (Sheet 1 of 2) Symbol Parameter Unit Notes OL / V OL1 Output Low Voltage 0.255 3 mA V OH1 Output High Voltage V_PROC_IO - 0.3 V_PROC_IO -3 mA V OL2 Output Low Voltage —...
Page 310 Electrical Characteristics Table 8-10. DC Output Characteristics (Sheet 2 of 2) Symbol Parameter Unit Notes OL / 0.75 × Output High Voltage V_PROC_IO -6 mA VOH_PECI V_PROC_IO VOL_HDA Output Low Voltage — 0.1 × VccHDA 1.5 mA VOL_JTAG Output Low Voltage 0.1 ×...
Page 311: Other Dc Characteristics
1.10 VccClkDMI DMI Clock Buffer Voltage .998 1.05 1.10 VccSPI 3.3 V Supply for SPI Controller Logic 3.14 3.47 ® 1.05 V Supply for Intel Management VccASW .998 1.05 1.10 Engine and Integrated LAN VccRTC (G3-S0) Battery Voltage — 3.47...
Page 312: Signal Groups
Electrical Characteristics Table 8-11. Other DC Characteristics (Sheet 2 of 2) Symbol Parameter Unit Notes C IN Input Capacitance – All Other — — F C = 1 MHz C OUT Output Capacitance — — F C = 1 MHz C I/O I/O Capacitance —...
Page 313: Lvds Interface: Functional Operating Range (Vccalvds = 1.8 V ±5%)
Electrical Characteristics INL and DNL measured and calculated according to VESA video signal standards. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage). Table 8-14. LVDS Interface: Functional Operating Range (VccALVDS = 1.8 V ±5%) Symbol Parameter Unit Differential Output Voltage Change in VOD between Complementary...
Page 314: Pci Express* Interface Timings
Electrical Characteristics AC Characteristics Table 8-16. PCI Express* Interface Timings Symbol Parameter Unit Figures Notes Transmitter and Receiver Timings Unit Interval – PCI Express* 399.88 400.12 Gen 1 (2.5 GT/s) Unit Interval – PCI Express* 199.9 200.1 Gen 2 (5.0 GT/s) Minimum Transmission Eye —...
Page 315: Hdmi Interface Timings (Ddp[D:b][3:0])Timings
Electrical Characteristics Table 8-17. HDMI Interface Timings (DDP[D:B][3:0])Timings Symbol Parameter Unit Figures Notes Transmitter and Receiver Timings Unit Interval 4000 Minimum Transmission Eye — TX-EYE Width D+/D- TX Out put Rise/Fall — 0.125 TX-RISE/Fall time TMDS — 0.25 Clock Jitter T-skew- Intra pair skew at source —...
Page 316: Displayport Interface Timings (Ddp[D:b][3:0])
Electrical Characteristics same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. Specified at the measurement point and measured over any 250 consecutive UIs. The test load documented in the PCI Express* specification 2.0 should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram).
Page 317: Displayport Aux Interface
Electrical Characteristics Table 8-20. DisplayPort Aux Interface Symbol Parameter Unit Aux unit interval µs AUX CH bus park time — — Aux_bus_park maximum allowable UI variation within Tcycle-to-cycle a single transaction at the connector 0.04 — jitter pins of a transmitting device maximum allowable UI variation within a single transaction at the connector 0.05...
Page 318: Lvds Interface Ac Characteristics At Various Frequencies
Electrical Characteristics Table 8-22. LVDS Interface AC characteristics at Various Frequencies (Sheet 1 of 2) Symbol Parameter Unit Figures Notes LVDS Low-to-High 1, Across receiver LLHT 0.25 0.75 Transition Time termination Figure 8-26 LVDS High-to-Low 1, Across receiver LHLT 0.25 0.75 Transition Time termination...
Page 319 Electrical Characteristics Table 8-22. LVDS Interface AC characteristics at Various Frequencies (Sheet 2 of 2) Symbol Parameter Unit Figures Notes Frequency = 85–MHz Transmitter Output TPPos0 -0.20 0.20 Pulse for Bit 0 Transmitter Output TPPos1 1.48 1.68 1.88 Pulse for Bit 1 Transmitter Output TPPos2 3.16...
Page 320: Crt Dac Ac Characteristics
Electrical Characteristics Table 8-23. CRT DAC AC Characteristics Parameter Units Notes Pixel Clock Frequency 1, 2, 8 (10-90% of black-to-white R, G, B Video Rise Time 0.25 — 1.25 transition, @ 400-MHz pixel clock) 1, 3, 8 (90-10% of white-to-black R, G, B Video Fall Time 0.25 —...
Page 321 Electrical Characteristics Table 8-24. Clock Timings (Sheet 2 of 4) Unit Parameter Notes Figure 48 MHz Flex Clock Period 20.32 21.34 8-11 High Time 7.02 12.51 8-11 Low Time 6.63 12.30 8-11 Duty Cycle Rising Edge Rate V/ns Falling Edge Rate V/ns Jitter (48MHz configured on —...
Page 322 s 8-20 t24_SML Rise time — 8-20 t25_SML Fall time — 8-20 ® HDA_BCLK (Intel High Definition Audio) Operating Frequency 24.0 Frequency Tolerance — Input Jitter (refer to Clock Chip t26a — Specification) t27a High Time (Measured at 0.75 Vcc) 18.75...
Page 323 Jitter analysis is performed using a standardized tool provided by the PCI SIG. Measurement methodology is defined in Intel document “PCI Express Reference Clock Jitter Measurements”. Note that this is not for CLKOUT_PCIE[7:0].
Page 324: Pci Interface Timing
Electrical Characteristics Table 8-25. PCI Interface Timing Parameter Units Notes Figure AD[31:0] Valid Delay 8-12 AD[31:0] Setup Time to PCICLK Rising — 8-13 AD[31:0] Hold Time from PCICLK Rising — 8-13 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, DEVSEL# 8-12 Valid Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#,...
Page 325: Universal Serial Bus Timing
Electrical Characteristics Table 8-26. Universal Serial Bus Timing Parameter Units Notes Full-speed Source (Note 7) 1, C L = 50 t100 USBPx+, USBPx- Driver Rise Time 8-17 1, C L = 50 t101 USBPx+, USBPx- Driver Fall Time 8-17 Source Differential Driver Jitter t102 - To Next Transition –3.5...
Page 326: Sata Interface Timings
Electrical Characteristics Measured from 10% to 90% of the data signal. Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s. Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s. Table 8-27. SATA Interface Timings Parameter Units Notes...
Page 327: Smbus And Smlink Timing
Electrical Characteristics Table 8-28. SMBus and SMLink Timing Parameter Units Notes Bus Free Time Between Stop and Start t130 — µs 8-20 Condition Bus Free Time Between Stop and Start t130SMLFM — µs 8-20 Condition Hold Time after (repeated) Start t131 Condition.
Page 328: Lpc Timing
Electrical Characteristics ® Table 8-29. Intel High Definition Audio Timing Parameter Units Notes Time duration for which HDA_SD is t143 — 8-23 valid before HDA_BCLK edge. Time duration for which HDA_SDO is t144 — 8-23 valid after HDA_BCLK edge. Setup time for HDA_SDIN[3:0] at rising t145 —...
Page 329: Spi Timings (20 Mhz)
Electrical Characteristics Table 8-32. SPI Timings (20 MHz) Parameter Units Notes Serial Clock Frequency - 20M Hz t180a 17.06 18.73 Operation Tco of SPI_MOSI with respect to serial t183a 8-22 clock falling edge at the host Setup of SPI_MISO with respect to t184a —...
Page 330: Spi Timings (50 Mhz)
Electrical Characteristics Table 8-34. SPI Timings (50 MHz) Parameter Units Notes Serial Clock Frequency - 50-MHz t180c 46.99 53.40 Operation Tco of SPI_MOSI with respect to serial t183c 8-22 clock falling edge at the host Setup of SPI_MISO with respect to t184c —...
Page 331: Power Sequencing And Reset Signal Timings
Electrical Characteristics Power Sequencing and Reset Signal Timings Table 8-36. Power Sequencing and Reset Signal Timings (Sheet 1 of 2) Parameter Units Notes 8-1, t200 VccRTC active to RTCRST# deassertion — 8-1, t200a RTCRST# deassertion to DPWROK high — 8-1, t200b VccDSW3_3 active to DPWROK high —...
Page 332 RTCRST# deassertion to VccRTC rail t236 — falling SLP_LAN# (or LANPHYPC) rising to t237 — Intel LAN Phy power high and stable DPWROK falling to any of VccDSW, 1, 13, t238 VccSUS, VccASW, VccASW3_3, or Vcc — 14, 15 falling...
Page 333 V_PROC_IO, VccCLKDMI, VccDIFFCLKN, VccVRM, VccDFTERM, VccSSC, VccALVDS (mobile ® only), VccTXLVDS (mobile only) and VccASW (if Intel ME only powered in S0). A Power rail is considered to be inactive when the rail is at its nominal voltage minus 5% or less.
Page 334: G3 W/Rtc Loss To S4/S5 (With Deep S4/S5 Support) Timing Diagram
Electrical Characteristics Power Management Timing Diagrams Figure 8-1. G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram S o u r c e D e s tin a tio n S ig n a l N a m e D e e p S 4 /S 5 S 5 /S 4 B o a rd...
Page 335: S5 To S0 Timing Diagram
Electrical Characteristics Figure 8-3. S5 to S0 Timing Diagram Source Dest Signal Name Board SLP_S5# Board SLP_S4# t203 Board SLP_S3# t204 Board SLP_A# Could already be high before this sequence begins (to support M3), but will never go high later than SLP_S3# Board SLP_LAN# Could already be high before this sequence begins (to support WOL),...
Page 336: S3/M3 To S0 Timing Diagram
Electrical Characteristics Figure 8-4. S3/M3 to S0 Timing Diagram Source Dest Signal Name Board SLP_S5# Board SLP_S4# Board SLP_S3# Board SLP_A# Board SLP_LAN# Board VccASW Board PROCPWRGD Serial VID CPU VRM CPU SVID Load Note: V_PROC_IO may go to Vboot at this time, but can also stay at 0V V_vid (default)
Page 337: S0 To S5 Timing Diagram
Electrical Characteristics Figure 8-6. S0 to S5 Timing Diagram Source Dest Signal Name L2/L3 DMI Message PCIe* normal PCIe Ports L2/L3 Devices operation Board SUS_STAT# t214 t215 Board PLTRST# t217 Board PROCPWRGD THRMTRIP# honored ignored t218 Board valid Output Clocks Board SLP_S3# t219...
Page 338: S4/S5 To Deep S4/S5 To G3 W/ Rtc Loss Timing Diagram
Electrical Characteristics Figure 8-7. S4/S5 to Deep S4/S5 to G3 w/ RTC Loss Timing Diagram S o u r c e D e s tin a t io n S ig n a l N a m e D e e p S 4 /S 5 S 4 / S 5 P C H B o a r d ( E C )
Page 339: Clock Cycle Time
Electrical Characteristics AC Timing Diagrams Figure 8-9. Clock Cycle Time Figure 8-10. Transmitting Position (Data to Strobe) CLKA/ CLKB Tppos0 YA/YB Tppos1 Tppos2 Tppos3 Tppos4 Tppos5 Tppos6 Figure 8-11. Clock Timing Period High Time 2.0V 0.8V Low Time Fall Time Rise Time Datasheet...
Page 340: Setup And Hold Times
Electrical Characteristics Figure 8-12. Valid Delay from Rising Clock Edge Clock 1.5V Valid Delay Output Figure 8-13. Setup and Hold Times Clock 1.5V Setup Time Hold Time Input Figure 8-14. Float Delay Input Float Delay Output Figure 8-15. Pulse Width Pulse Width Datasheet...
Page 341: Output Enable Delay
Electrical Characteristics Figure 8-16. Output Enable Delay Clock 1.5V Output Enable Delay Output Figure 8-17. USB Rise and Fall Times Rise Time Fall Time Differential Data Lines Low-speed: 75 ns at C = 50 pF, 300 ns at C = 350 pF Full-speed: 4 to 20 ns at C = 50 pF High-speed: 0.8 to 1.2 ns at C...
Page 342: Usb Eop Width
Electrical Characteristics Figure 8-19. USB EOP Width Tperiod Data Crossover Differential Level Data Lines Width Figure 8-20. SMBus Transaction SMBCLK t135 t133 t131 t134 t132 SMBDATA t130 Figure 8-21. SMBus Timeout Start Stop t137 t138 t138 SMBCLK SMBDATA Datasheet...
Page 343: Spi Timings
Electrical Characteristics Figure 8-22. SPI Timings t188 t189 SPI_CLK t183 SPI_MOSI t184 t185 SPI_MISO t186 t187 SPI_CS# ® Figure 8-23. Intel High Definition Audio Input and Output Timings HDA_BIT_CLK HDA_SDOUT t143 t144 t143 t144 HDA_SDIN[3:0] t145 t146 Datasheet...
Page 344: Dual Channel Interface Timings
Electrical Characteristics Figure 8-24. Dual Channel Interface Timings tDQSL tDQS DQ[7:0] Figure 8-25. Dual Channel Interface Timings D Q [7 : 0 ] tDV W tDQ S Q tQ H tDQ S Q Figure 8-26. LVDS Load and Transition Times Datasheet...
Page 345: Transmitting Position (Data To Strobe)
Electrical Characteristics Figure 8-27. Transmitting Position (Data to Strobe) CLKA/ CLKB Tppos0 YA/YB Tppos1 Tppos2 Tppos3 Tppos4 Tppos5 Tppos6 Figure 8-28. PCI Express Transmitter Eye Datasheet...
Page 346: Pci Express Receiver Eye
Electrical Characteristics Figure 8-29. PCI Express Receiver Eye TS-Diff = 0mV D+/D- Crossing point RS-Diffp-p-Min>175mV .4 UI =T RX-EYE min Datasheet...
Page 347: Measurement Points For Differential Waveforms
Electrical Characteristics Figure 8-30. Measurement Points for Differential Waveforms. Differential Clock – Single Ended Measurements V max = 1.15V V max = 1.15V Clock# Vcross max = Vcross max = 550mV 550mV Vcross min = 300 mV Vcross min = 300 mV Clock V min = -0.30V V min = -0.30V...
Page 348: Pch Test Load
Electrical Characteristics Figure 8-31. PCH Test Load VccASW3_3 Figure 8-32. Controller Link Receive Timings t191 CL_CLK1 t190 t193 t194 CL_DATA1 Figure 8-33. Controller Link Receive Slew Rate t192 t192 CL_Vref + 50mV CL_Vref CL_Vref – 50mV CL_CLK1 / CL_DATA1 § § Datasheet...
Page 349 Register and Memory Mapping Register and Memory Mapping The PCH contains registers that are located in the processor’s I/O space and memory space and sets of PCI configuration registers that are located in PCI configuration space. This chapter describes the PCH I/O and memory maps at the register-set level. Register access is also described.
Page 350: Pci Devices And Functions
® Bus 0:Device 22:Function 0 Intel Management Engine Interface #1 Bus 0:Device 22:Function 1 Intel Management Engine Interface #2 Bus 0:Device 22:Function 2 IDE-R Bus 0:Device 22:Function 3 NOTES: The PCI-to-LPC bridge contains registers that control LPC, Power Management, System Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA.
Page 351: Address Map
Register and Memory Mapping PCI Configuration Map Each PCI function on the PCH has a set of PCI configuration registers. The register address map tables for these register sets are included at the beginning of the chapter for the particular function. Configuration Space registers are accessed through configuration cycles on the PCI bus by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus Specification, Revision 2.3.
Page 352: Fixed I/O Ranges Decoded By Intel
Register and Memory Mapping ® Table 9-2. Fixed I/O Ranges Decoded by Intel PCH (Sheet 1 of 2) Read Target Write Target Internal Unit Address 00h–08h DMA Controller DMA Controller 09h–0Eh RESERVED DMA Controller DMA Controller DMA Controller 10h–18h DMA Controller DMA Controller 19h–1Eh...
Page 353 Register and Memory Mapping ® Table 9-2. Fixed I/O Ranges Decoded by Intel PCH (Sheet 2 of 2) Read Target Write Target Internal Unit Address 89h–8Bh DMA Controller DMA Controller 8Ch–8Eh DMA Controller DMA Controller and LPC or PCI 08Fh...
Page 354: Variable I/O Decode Ranges
Register and Memory Mapping 9.3.2 Variable I/O Decode Ranges Table 9-3 shows the Variable I/O Decode Ranges. They are set using Base Address Registers (BARs) or other configuration bits in the various PCI configuration spaces. The PNP software (PCI or ACPI) can use their configuration mechanisms to set and adjust these values.
Page 355: Memory Decode Ranges From Processor Perspective
Register and Memory Mapping Memory Map Table 9-4 shows (from the processor perspective) the memory ranges that the PCH decodes. Cycles that arrive from DMI that are not directed to any of the internal memory targets that decode directly from DMI will be driven out on PCI unless the Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0).
Page 356 1 KB anywhere in 4-GB USB EHCI Enable using standard PCI mechanism (Device range Controller #2 26, Function 0/7) ® Intel High 16 KB anywhere in 64-bit Enable using standard PCI mechanism (Device Definition Audio addressing space 27, Function 0) Host Controller BIOS determines the “fixed”...
Page 357 Register and Memory Mapping 9.4.1 Boot-Block Update Scheme The PCH supports a “top-block swap” mode that has the PCH swap the top block in the Firmware Hub (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs).
Page 358 Register and Memory Mapping Datasheet...
Page 359: Chipset Configuration Register Memory Map (Memory Space)
Chipset Configuration Registers Chipset Configuration Registers This section describes all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express*). It contains the root complex register block, which describes the behavior of the upstream internal link.
Page 360 Chipset Configuration Registers Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 4) Offset Mnemonic Register Name Default Type R/W, RO, 2020h–2023h V1CTL VC 1 Resource Control 00000000h R/WL 2026h–2027h V1STS VC 1 Resource Status 0000h R/WL. 2030h–2033h CIR31 Chipset Initialization Register 31...
Page 361 Chipset Configuration Registers Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 4) Offset Mnemonic Register Name Default Type 3314h–3317h CIR7 Chipset Initialization Register 7 00000000h 3318h–331Bh PM_CFG Power Management Configuration 00000000h 3324h–3327h CIR8 Chipset Initialization Register 8 00000000h 332Ch–332Fh DEEP_S4_POL...
Page 362 Chipset Configuration Registers Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 4 of 4) Offset Mnemonic Register Name Default Type – 3A80 3A83h CIR27 Chipset Initialization Register 27 00000000h – 3A84 3A87h CIR28 Chipset Initialization Register 28 00000000h –...
Page 363 Chipset Configuration Registers 10.1.2 RPC—Root Port Configuration Register Offset Address: 0400–0403h Attribute: R/W, RO Default Value: 0000000yh (y = 00xxb) Size: 32-bit Description 31:12 Reserved GbE Over PCIe Root Port Enable (GBEPCIERPEN) — R/W. 0 = GbE MAC/PHY communication is not enabled over PCI Express. 1 = The PCI Express port selected by the GBEPCIEPORTSEL register will be used for GbE MAC/PHY over PCI Express communication The default value for this register is set by the GBE_PCIE_EN soft strap.
Page 364 Chipset Configuration Registers 10.1.3 RPFN—Root Port Function Number and Hide for PCI Express* Root Ports Offset Address: 0404–0407h Attribute: R/WO, RO Default Value: 76543210h Size: 32-bit For the PCI Express root ports, the assignment of a function number to a root port is not fixed.
Page 365 Chipset Configuration Registers Description Root Port 3 Function Number (RP3FN) — R/WO. These bits set the function 10:8 number for PCI Express Root Port 3. This root port function number must be a unique value from the other root port function numbers Root Port 2 Config Hide (RP2CH) —...
Page 366 Chipset Configuration Registers 10.1.6 CIR3—Chipset Initialization Register 3 Offset Address: 1100–1101h Attribute: Default Value: 0000h Size: 16-bit Description 15:0 CIR3 Field 1 — R/W. BIOS must program this field to 6000h. 10.1.7 TRSR—Trap Status Register Offset Address: 1E00–1E03h Attribute: R/WC, RO Default Value: 00000000h Size:...
Page 367 Chipset Configuration Registers 10.1.9 TWDR—Trapped Write Data Register Offset Address: 1E18–1E1Fh Attribute: Default Value: 0000000000000000h Size: 64-bit This register saves the data from I/O write cycles that are trapped for software to read. Description 63:32 Reserved Trapped I/O Data (TIOD) — RO. DWord of I/O write data. This field is undefined 31:0 after trapping a read cycle.
Page 368 Chipset Configuration Registers 10.1.11 V0CTL—Virtual Channel 0 Resource Control Register Offset Address: 2014–2017h Attribute: R/WL, RO Default Value: 80000011h Size: 32-bit Description Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and cannot be disabled. 30:27 Reserved Virtual Channel Identifier (ID) —...
Page 369 Chipset Configuration Registers 10.1.13 V1CTL—Virtual Channel 1 Resource Control Register Offset Address: 2020–2023h Attribute: R/W, RO, R/WL Default Value: 00000000h Size: 32-bit Description Virtual Channel Enable (EN) — R/W. Enables the VC when set. Disables the VC when cleared. 30:28 Reserved Virtual Channel Identifier (ID) —...
Page 370 Chipset Configuration Registers 10.1.16 CIR32—Chipset Initialization Register 32 Offset Address: 2040–2043h Attribute: R/WL, RO Default Value: 00000000h Size: 32-bit Description CIR32 Field 0— R/WL. BIOS must set this field. These bits are locked if the 31:0 TCLOCKDN bit (RCBA+0050h:bit 31) is set. 10.1.17 CIR1—Chipset Initialization Register 1 Offset Address: 2088–208Bh...
Page 371 Chipset Configuration Registers 10.1.19 LCAP—Link Capabilities Register Offset Address: 21A4–21A7h Attribute: R/WO, RO Default Value: 00012C42h Size: 32-bit Description 31:18 Reserved 17:15 (Desktop Reserved Only) 17:15 (Mobile L1 Exit Latency (EL1) — RO. L1 is supported on DMI. Only) L0s Exit Latency (EL0) — R/WO. This field indicates that exit latency is 128 ns to 14:12 less than 256 ns.
Page 372 Chipset Configuration Registers 10.1.21 LSTS—Link Status Register Offset Address: 21AA–21ABh Attribute: Default Value: 0042h Size: 16-bit Description 15:10 Reserved Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b). Current Link Speed (LS) — RO. 0001b = 2.5 Gb/s 0010b = 5.0 Gb/s 10.1.22 DMIC—DMI Control Register...
Page 373 Chipset Configuration Registers 10.1.25 DMC—DMI Miscellaneous Control Register Offset Address: 2304–2307h Attribute: Default Value: 00000000h Size: 32-bit Description 31:0 DMC Field 1— R/W. BIOS must program this field to C0388400h. 10.1.26 CIR6—Chipset Initialization Register 6 Offset Address: 2314–2317h Attribute: Default Value: 0A000000h Size: 32-bit...
Page 374 Chipset Configuration Registers 10.1.28.1 DMI IOBP Indexed Registers 10.1.28.1.1 DIOBPIR1—DMI IOBP Indexed Register 1 IOBP Index: EBxx4000h Attribute: Default Value: Size: 32-bit Description 31:0 DIOBPIR1— R/W. BIOS may write to this bit field. 10.1.28.1.2 DIOBPIR2—DMI IOBP Indexed Register 2 IOBP Index: EBxx4002h Attribute: Default Value:...
Page 375 Chipset Configuration Registers 10.1.28.1.7 DIOBPIR7—DMI IOBP Indexed Register 7 IOBP Index: EBxx40A1h Attribute: Default Value: Size: 32-bit Description 31:0 DIOBPIR7— R/W. BIOS may write to this bit field. 10.1.28.1.8 DIOBPIR8—DMI IOBP Indexed Register 8 IOBP Index: EBxx40B1h Attribute: Default Value: Size: 32-bit Description...
Page 376 Chipset Configuration Registers 10.1.28.2 PCIe IOBP Indexed Registers 10.1.28.2.1 PIOBPIR1—PCIe IOBP Indexed Register 1 IOBP Index: ECxx0408h Attribute: Default Value: Size: 32-bit Description 31:0 PIOBPIR1— R/W. BIOS may write to this bit field. 10.1.28.2.2 PIOBPIR2—PCIe IOBP Indexed Register 2 IOBP Index: ECxx0503h Attribute: Default Value:...
Page 377 Chipset Configuration Registers 10.1.28.2.7 PIOBPIR7—PCIe IOBP Indexed Register 7 IOBP Index: ECxx0A03h Attribute: Default Value: Size: 32-bit Description 31:0 PIOBPIR7— R/W. BIOS may write to this bit field. 10.1.28.2.8 PIOBPIR8—PCIe IOBP Indexed Register 8 IOBP Index: ECxx4000h Attribute: Default Value: Size: 32-bit Description...
Page 378 Chipset Configuration Registers 10.1.28.2.13PIOBPIR13—PCIe IOBP Indexed Register 13 IOBP Index: ECxx40A1h Attribute: Default Value: Size: 32-bit Description 31:0 PIOBPIR13— R/W. BIOS may write to this bit field. 10.1.28.2.14PIOBPIR14—PCIe IOBP Indexed Register 14 IOBP Index: ECxx40B1h Attribute: Default Value: Size: 32-bit Description 31:0 PIOBPIR14—...
Page 379 Chipset Configuration Registers 10.1.28.2.19 PIOBPIR19—PCIe IOBP Indexed Register 19 IOBP Index: ECxx7F62h Attribute: Default Value: Size: 32-bit Description 31:0 PIOBPIR19— R/W. BIOS may write to this bit field. 10.1.28.2.20 PIOBPIR20—PCIe IOBP Indexed Register 20 IOBP Index: ECxx7F64h Attribute: Default Value: Size: 32-bit Description...
Page 380 Chipset Configuration Registers 10.1.30 D31IP—Device 31 Interrupt Pin Register Offset Address: 3100–3103h Attribute: R/W, RO Default Value: 03243200h Size: 32-bit Description 31:28 Reserved Thermal Throttle Pin (TTIP) — R/W. Indicates which pin the Thermal Throttle controller drives as its interrupt 0h = No interrupt 1h = INTA# 27:24...
Page 381 Chipset Configuration Registers 10.1.31 D30IP—Device 30 Interrupt Pin Register Offset Address: 3104–3107h Attribute: Default Value: 00000000h Size: 32-bit Description 31:4 Reserved PCI Bridge Pin (PIP) — RO. Currently, the PCI bridge does not generate an interrupt, so this field is read-only and 0. 10.1.32 D29IP—Device 29 Interrupt Pin Register Offset Address: 3108–310Bh...
Page 382 Chipset Configuration Registers Description PCI Express* #6 Pin (P6IP) — R/W. Indicates which pin the PCI Express* port #6 drives as its interrupt. 0h = No interrupt 1h = INTA# 23:20 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved PCI Express #5 Pin (P5IP) —...
Page 383 Description 31:4 Reserved ® ® Intel High Definition Audio Pin (ZIP) — R/W. Indicates which pin the Intel High Definition Audio controller drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–Fh = Reserved...
Page 384 2h = INTB# 3h = INTC# 4h = INTD# 5h–Fh = Reserved ® Intel MEI #2 Pin (MEI2IP) — R/W. Indicates which pin the Management Engine Interface #2 drives as its interrupt 0h = No Interrupt 1h = INTA# 2h = INTB#...
Page 385 Chipset Configuration Registers 10.1.38 D31IR—Device 31 Interrupt Route Register Offset Address: 3140–3141h Attribute: Default Value: 3210h Size: 16-bit Description Reserved Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC#...
Page 386 Chipset Configuration Registers 10.1.39 D30IR—Device 30 Interrupt Route Register Offset Address: 3142–3143h Attribute: Default Value: 0000h Size: 16-bit Description 15:0 Reserved. No interrupts generated from Device 30. 10.1.40 D29IR—Device 29 Interrupt Route Register Offset Address: 3144–3145h Attribute: Default Value: 3210h Size: 16-bit Description...
Page 387 Chipset Configuration Registers 10.1.41 D28IR—Device 28 Interrupt Route Register Offset Address: 3146–3147h Attribute: Default Value: 3210h Size: 16-bit Description Reserved Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC#...
Page 388 Chipset Configuration Registers 10.1.42 D27IR—Device 27 Interrupt Route Register Offset Address: 3148–3149h Attribute: Default Value: 3210h Size: 16-bit Description Reserved Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC#...
Page 389 Chipset Configuration Registers 10.1.43 D26IR—Device 26 Interrupt Route Register Offset Address: 314C–314Fh Attribute: Default Value: 3210h Size: 16-bit Description Reserved Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 26 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC#...
Page 390 Chipset Configuration Registers 10.1.44 D25IR—Device 25 Interrupt Route Register Offset Address: 3150–3151h Attribute: Default Value: 3210h Size: 16-bit Description Reserved Interrupt D Pin Route (IDR): — R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 25 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC#...
Page 391 Chipset Configuration Registers 10.1.45 D22IR—Device 22 Interrupt Route Register Offset Address: 315C–315Fh Attribute: Default Value: 3210h Size: 16-bit Description Reserved Interrupt D Pin Route (IDR): — R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 22 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC#...
Page 392 Chipset Configuration Registers 10.1.46 OIC—Other Interrupt Control Register Offset Address: 31FE–31FFh Attribute: Default Value: 0000h Size: 16-bit Description 15:10 Reserved Coprocessor Error Enable (CEN) — R/W. 0 = FERR# will not generate IRQ13 nor IGNNE#. 1 = If FERR# is low, the PCH generates IRQ13 internally and holds it until an I/O port F0h write.
Page 393 Intel Management Engine generates a Host reset with power cycling. Software clears this bit by writing a 1 to this bit position. Intel ME WAKE STATUS (ME_WAKE_STS) — R/WC. This bit is set when the Intel Management Engine generates a Non-Maskable wake event, and is not affected by any other enable bit.
Page 394 Chipset Configuration Registers 10.1.49 PM_CFG—Power Management Configuration Offset Address: 3318–331Bh Attribute: Default Value: 00000000h Size: 32-bit Description 31:27 Reserved. 26:24 PM_CFG Field 1 — R/W. BIOS must program this field to 101b. 23:22 Reserved. RTC Wake from Deep S4/S5 Disable (RTC_DS_WAKE_DIS)— R/W. When set, this bit disables RTC wakes from waking the system from Deep S4/S5.
Page 395 Chipset Configuration Registers 10.1.50 CIR8—Chipset Initialization Register 8 Offset Address: 3324–3327h Attribute: Default Value: 00000000h Size: 32-bit Description 31:0 CIR8 Field 1 — R/W. BIOS must program this field to 04000000h. 10.1.51 DEEP_S4_POL—Deep S4 Power Policies Offset Address: 332C–332Fh Attribute: Default Value: 00000000h Size:...
Page 396 Chipset Configuration Registers 10.1.54 CIR11—Chipset Initialization Register 11 Offset Address: 3344–3347h Attribute: Default Value: 00000000h Size: 32-bit Description 31:2 Reserved CIR11 Field 1 — R/W. BIOS must program this field to 10b. 10.1.55 CIR33—Chipset Initialization Register 33 Offset Address: 3348–334Bh Attribute: Default Value: 00000000h...
Page 397 Chipset Configuration Registers 10.1.57 CIR12—Chipset Initialization Register 12 Offset Address: 3360–3363h Attribute: Default Value: 00000000h Size: 32-bit Description 31:0 CIR12 Field 1 — R/W. BIOS must program this field to 0001C000h. 10.1.58 CIR14—Chipset Initialization Register 14 Offset Address: 3368–336Bh Attribute: Default Value: 00000000h Size:...
Page 398 Chipset Configuration Registers 10.1.63 CIR17—Chipset Initialization Register 17 Offset Address: 33A0–33A3h Attribute: Default Value: 00000000h Size: 32-bit Description 31:0 CIR17 Field 1 — R/W. BIOS must program this field to 00000800h. 10.1.64 CIR23—Chipset Initialization Register 23 Offset Address: 33B0–33B3h Attribute: Default Value: 00000000h Size:...
Page 399 Chipset Configuration Registers 10.1.67 CIR20—Chipset Initialization Register 20 Offset Address: 33CC–33CFh Attribute: Default Value: 00000000h Size: 32-bit Description 31:0 CIR20 Field 1 — R/W. BIOS must program this field to 24653002h. 10.1.68 CIR21—Chipset Initialization Register 21 Offset Address: 33D0–33D3h Attribute: Default Value: 00000000h Size:...
Page 400 Chipset Configuration Registers 10.1.70 RC—RTC Configuration Register Offset Address: 3400–3403h Attribute: R/W, R/WLO Default Value: 00000000h Size: 32-bit Description 31:5 Reserved Upper 128 Byte Lock (UL) — R/WLO. 0 = Bytes not locked. 1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be accessed.
Page 401 NOTE: Booting to PCI is intended for debug/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will ® not affect SPI accesses initiated by Intel Management Engine or Integrated GbE LAN. Server Error Reporting Mode (SERM) — R/W.
Page 402 Chipset Configuration Registers Description Alternate Access Mode Enable (AME) — R/W. 0 = Disabled. 1 = Alternate access read only registers can be written, and write only registers can be read. Before entering a low power state, several registers from powered down parts may need to be saved.
Page 403 Chipset Configuration Registers 10.1.73 BUC—Backed Up Control Register Offset Address: 3414–3414h Attribute: Default Value: 0000000xb Size: 8-bit All bits in this register are in the RTC well and only cleared by RTCRST#. Description Reserved LAN Disable — R/W. 0 = LAN is Enabled 1 = LAN is Disabled.
Page 404 Chipset Configuration Registers Description PCI Express 7 Disable (PE7D) — R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express port #7 is enabled. 1 = PCI Express port #7 is disabled. PCI Express* 6 Disable (PE6D) —...
Page 405 Chipset Configuration Registers Description PCI Express 7 Disable (PE7D) — R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express port #7 is enabled. 1 = PCI Express port #7 is disabled. PCI Express* 6 Disable (PE6D) —...
Page 406 Description ® Intel High Definition Audio Disable (HDAD) — R/W. Default is 0. ® 0 = The Intel High Definition Audio controller is enabled. ® 1 = The Intel High Definition Audio controller is disabled and its PCI configuration space is not accessible.
Page 407 8-bit Description Function Disable SUS Well Lockdown (FDSWL)— R/W03 0 = FDSW registers are not locked down 1 = FDSW registers are locked down ® NOTE: This bit must be set when Intel Active Management Technology is enabled. Reserved Datasheet...
Page 408 ® Intel MEI #2 Disable (MEI2D) —R/W. Default is 0. 0 = Intel MEI controller #2 (D22:F1) is enabled. 1 = Intel MEI controller #2 (D22:F1) is disabled. Intel MEI #1 Disable (MEI1D) —R/W. Default is 0. 0 = Intel MEI controller #1 (D22:F0) is enabled.
Page 409 Chipset Configuration Registers 10.1.79 MISCCTL—Miscellaneous Control Register Offset Address: 3590–3594h Attribute: Default Value: 00000000h Size: 32-bit This register is in the suspend well. This register is not reset on D3-to-D0, HCRESET nor core well reset. Description 31:2 Reserved. EHCI 2 USBR Enable — R/W. When set, this bit enables support for the USB-r redirect device on the EHCI controller in Device 26.
Page 410 Chipset Configuration Registers 10.1.80 USBOCM1—Overcurrent MAP Register 1 Offset Address: 35A0–35A3h Attribute: R/W0 Default Value: C0300C03h Size: 32-bit All bits in this register are in the Resume Well and is only cleared by RSMRST#. Description OC3 Mapping Each bit position maps OC3# to a set of ports as follows: The OC3# pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
Page 411 Chipset Configuration Registers 10.1.81 USBOCM2—Overcurrent MAP Register 2 Offset Address: 35A4–35A7h Attribute: R/W0 Default Value: Size: 32-bit All bits in this register are in the Resume Well and is only cleared by RSMRST# Description 31:30 Reserved OC7 Mapping Each bit position maps OC7# to a set of ports as follows: The OC7# pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
Page 412 Chipset Configuration Registers 10.1.82 RMHWKCTL—Rate Matching Hub Wake Control Register Offset Address: 35B0–35B3h Attribute: Default Value: 00000000h Size: 32-bit All bits in this register are in the Resume Well and is only cleared by RSMRST#. Description 31:10 Reserved RMH 2 Inherit EHCI2 Wake Control Settings: When this bit is set, the RMH behaves as if bits 6:4 of this register reflect the appropriate bits of EHCI PORTSC0 bits 22:20.
Page 413 Chipset Configuration Registers Description RMH 1 Upstream Wake on OC Disable This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables the port to be sensitive to over-current conditions as system wake-up events.
Page 414 Chipset Configuration Registers Default Value: 00000000h Size: 32-bit Description 31:0 CIR27 Field 1 — R/W. BIOS must program this field to 01041041h. 10.1.87 CIR28—Chipset Initialization Register 28 Offset Address: 3A84–3A87h Attribute: Default Value: 00000000h Size: 32-bit Description 31:25 Reserved CIR28 Field 3 — R/W. BIOS may write to this bit field. 23:19 Reserved CIR28 Field 2 —...
Page 415: Pci Bridge Register Address Map (Pci-Pci-D30:F0)
PCI-to-PCI Bridge Registers (D30:F0) PCI-to-PCI Bridge Registers (D30:F0) The PCH PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements the buffering and control logic between PCI and the backbone. The arbitration for the PCI bus is handled by this PCI device. 11.1 PCI Configuration Registers (D30:F0) Note:...
Page 416 Attribute: Default Value: 8086h Size: 16 bits Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 11.1.2 DID— Device Identification Register (PCI-PCI—D30:F0) Offset Address: 02h–03h Attribute: Default Value: See bit description...
Page 417 PCI-to-PCI Bridge Registers (D30:F0) Description Memory Space Enable (MSE) — R/W. Controls the response as a target for memory cycles targeting PCI. 0 = Disable 1 = Enable I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles targeting PCI.
Page 418 PCI-to-PCI Bridge Registers (D30:F0) Description Signaled System Error (SSE) — R/WC. Several internal and external sources of the bridge can cause SERR#. The first class of errors is parity errors related to the backbone. The PCI bridge captures generic data parity errors (errors it finds on the backbone) as well as errors returned on backbone cycles where the bridge was the master.
Page 419 Attribute: Default Value: See bit description Size: 8 bits Description ® Revision ID — RO. See the Intel 6 Series Chipset Specification Update for the value of the RID Register. 11.1.6 CC—Class Code Register (PCI-PCI—D30:F0) Offset Address: 09h–0Bh Attribute: Default Value:...
Page 420 PCI-to-PCI Bridge Registers (D30:F0) 11.1.7 PMLT—Primary Master Latency Timer Register (PCI-PCI—D30:F0) Offset Address: 0Dh Attribute: Default Value: Size: 8 bits Description Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base Specification, Revision 1.0a. Reserved 11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) Offset Address: 0Eh Attribute: Default Value:...
Page 421 PCI-to-PCI Bridge Registers (D30:F0) 11.1.10 SMLT—Secondary Master Latency Timer Register (PCI-PCI—D30:F0) Offset Address: 1Bh Attribute: Default Value: Size: 8 bits This timer controls the amount of time the PCH PCI-to-PCI bridge will burst data on its secondary interface. The counter starts counting down from the assertion of FRAME#. If the grant is removed, then the expiration of this counter will result in the deassertion of FRAME#.
Page 422 PCI-to-PCI Bridge Registers (D30:F0) 11.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0) Offset Address: 1Eh Attribute: R/WC, RO – Default Value: 0280h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect.
Page 423 PCI-to-PCI Bridge Registers (D30:F0) 11.1.13 MEMBASE_LIMIT—Memory Base and Limit Register (PCI-PCI—D30:F0) Offset Address: 20h–23h Attribute: Default Value: 00000000h Size: 32 bits This register defines the base and limit, aligned to a 1-MB boundary, of the non- prefetchable memory area of the bridge. Accesses that are within the ranges specified in this register will be sent to PCI if CMD.MSE is set.
Page 424 PCI-to-PCI Bridge Registers (D30:F0) 11.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits Register (PCI-PCI—D30:F0) Offset Address: 28h–2Bh Attribute: Default Value: 00000000h Size: 32 bits Description Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the 31:0 prefetchable address base. 11.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits Register (PCI-PCI—D30:F0)
Page 425 PCI-to-PCI Bridge Registers (D30:F0) 11.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0) Offset Address: 3Eh Attribute: R/WC, RO, R/W – Default Value: 0000h Size: 16 bits Description 15:12 Reserved Discard Timer SERR# Enable (DTE) — R/W. Controls the generation of SERR# on the primary interface in response to the DTS bit being set: 0 = Do not generate SERR# on a secondary timer discard 1 = Generate SERR# in response to a secondary timer discard Discard Timer Status (DTS) —...
Page 426 PCI-to-PCI Bridge Registers (D30:F0) Description VGA Enable (VGAE) — R/W. When set to a 1, the PCH PCI bridge forwards the following transactions to PCI regardless of the value of the I/O base and limit registers. The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE (D30:F0:04 bit 0) being set.
Page 427 PCI-to-PCI Bridge Registers (D30:F0) 11.1.20 SPDH—Secondary PCI Device Hiding Register (PCI-PCI—D30:F0) Offset Address: 40h–41h Attribute: R/W, RO Default Value: 0000h Size: 16 bits This register allows software to hide the PCI devices, either plugged into slots or on the motherboard. Description 15:4 Reserved...
Page 428 PCI-to-PCI Bridge Registers (D30:F0) Description Maximum Delayed Transactions (MDT) — R/W. Controls the maximum number of delayed transactions that the PCH PCI bridge will run. Encodings are: 00 =) 2 Active, 5 pending 01 =) 2 active, no pending 10 =) 1 active, no pending 11 =) Reserved Reserved Auto Flush After Disconnect Enable (AFADE) —...
Page 429 PCI-to-PCI Bridge Registers (D30:F0) 11.1.22 BPS—Bridge Proprietary Status Register (PCI-PCI—D30:F0) Offset Address: 48h Attribute: R/WC, RO – Default Value: 00000000h Size: 32 bits Description 31:17 Reserved PERR# Assertion Detected (PAD) — R/WC. This bit is set by hardware whenever the PERR# pin is asserted on the rising edge of PCI clock.
Page 430 PCI-to-PCI Bridge Registers (D30:F0) 11.1.23 BPC—Bridge Policy Configuration Register (PCI-PCI—D30:F0) Offset Address: 4Ch–4Fh Attribute: Default Value: 10001200h Size: 32 bits Description 31:30 Reserved Subtractive Decode Compatibility Device ID (SDCDID) — R/W: When '0', this function shall report a Device ID of 244Eh for desktop. When set to '1', this function shall report the device Device ID value assigned to the PCI-to-PCI Bridge in Section If subtractive decode (SDE) is enabled, having this bit as '0' allows the function to...
Page 431 PCI-to-PCI Bridge Registers (D30:F0) Description Subtractive Decode Policy (SDP) — R/W. 0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any other device on the backbone (primary interface) to the PCI bus (secondary interface).
Page 432 PCI-to-PCI Bridge Registers (D30:F0) 11.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) Offset Address: 54h Attribute: R/WO – Default Value: 00000000h Size: 32 bits Description Subsystem Identifier (SID) — R/WO. Indicates the subsystem as identified by the 31:16 vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset).
Page 433: Gigabit Lan Configuration Registers Address Map
Gigabit LAN Configuration Registers Gigabit LAN Configuration Registers 12.1 Gigabit LAN Configuration Registers (Gigabit LAN — D25:F0) Note: Register address locations that are not shown in Table 12-1 should be treated as Reserved. Table 12-1. Gigabit LAN Configuration Registers Address Map (Gigabit LAN —D25:F0) (Sheet 1 of 2) Offset Mnemonic...
Page 434 Size: 16 bits Description Vendor ID — RO. This is a 16-bit value assigned to Intel. The field may be auto-loaded 15:0 from the NVM at address 0Dh during init time depending on the “Load Vendor/Device ID” bit field in NVM word 0Ah with a default value of 8086h.
Page 435 Gigabit LAN Configuration Registers 12.1.3 PCICMD—PCI Command Register (Gigabit LAN—D25:F0) Address Offset: 04h–05h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Description 15:11 Reserved Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled Hot- Plug and power management events. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or power management and MSI is not enabled.
Page 436 Gigabit LAN Configuration Registers 12.1.4 PCISTS—PCI Status Register (Gigabit LAN—D25:F0) Address Offset: 06h Attribute: R/WC, RO – Default Value: 0010h Size: 16 bits Description Detected Parity Error (DPE) — R/WC. 0 = No parity error detected. 1 = Set when the Gb LAN controller receives a command or data from the backbone with a parity error.
Page 437 Attribute: Default Value: See bit description Size: 8 bits Description ® Revision ID — RO. See the Intel 6 Series Chipset Specification Update for the value of the RID Register. 12.1.6 CC—Class Code Register (Gigabit LAN—D25:F0) Address Offset: 09h Attribute: –...
Page 438 Gigabit LAN Configuration Registers 12.1.10 MBARA—Memory Base Address Register A (Gigabit LAN—D25:F0) Address Offset: 10h Attribute: R/W, RO – Default Value: 00000000h Size: 32 bits The internal CSR registers and memories are accessed as direct memory mapped offsets from the base address register. SW may only access whole DWord at a time. Description Base Address (BA) —...
Page 439 Gigabit LAN Configuration Registers 12.1.12 MBARC—Memory Base Address Register C (Gigabit LAN—D25:F0) Address Offset: 18h Attribute: R/W, RO – Default Value: 00000001h Size: 32 bits Internal registers, and memories, can be accessed using I/O operations. There are two 4B registers in the I/O mapping window: Addr Reg and Data Reg. Software may only access a DWord at a time.
Page 440 Gigabit LAN Configuration Registers 12.1.16 CAPP—Capabilities List Pointer Register (Gigabit LAN—D25:F0) Address Offset: 34h Attribute: Default Value: Size: 8 bits Description Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the capabilities list is at C8h in configuration space. 12.1.17 INTR—Interrupt Information Register (Gigabit LAN—D25:F0)
Page 441 Gigabit LAN Configuration Registers 12.1.20 PMC—PCI Power Management Capabilities Register (Gigabit LAN—D25:F0) Address Offset: CAh Attribute: – Default Value: See bit descriptions Size: 16 bits Function Level Reset: No (Bits 15:11 only) Description PME_Support (PMES) — RO. This five-bit field indicates the power states in which the function may assert PME#.
Page 442 Gigabit LAN Configuration Registers 12.1.21 PMCS—PCI Power Management Control and Status Register (Gigabit LAN—D25:F0) Address Offset: CCh Attribute: R/WC, R/W, RO – Default Value: See bit description Size: 16 bits Function Level Reset: No (Bit 8 only) Description PME Status (PMES) — R/WC. This bit is set to 1 when the function detects a wake-up event independent of the state of the PMEE bit.
Page 443 Gigabit LAN Configuration Registers 12.1.22 DR—Data Register (Gigabit LAN—D25:F0) Address Offset: CFh Attribute: Default Value: See bit description Size: 8 bits Description Reported Data (RD) — RO. This register is used to report power consumption and heat dissipation. This register is controlled by the Data_Select field in the PMCS (Offset CCh, bits 12:9), and the power scale is reported in the Data_Scale field in the PMCS (Offset CCh, bits 14:13).
Page 444 Gigabit LAN Configuration Registers 12.1.25 MADDL—Message Address Low Register (Gigabit LAN—D25:F0) Address Offset: D4h–D7h Attribute: Default Value: See bit description Size: 32 bits Description Message Address Low (MADDL) — R/W. Written by the system to indicate the lower 31:0 32 bits of the address to use for the MSI memory write transaction. The lower two bits will always return 0 regardless of the write operation.
Page 445 Gigabit LAN Configuration Registers 12.1.29 FLRCLV—Function Level Reset Capability Length and Version (Gigabit LAN—D25:F0) Address Offset: E2h–E3h Attribute: R/WO, RO Default Value: See Description. Size: 16 bits Function Level Reset: No (Bits 9:8 Only When FLRCSSEL = 0) When FLRCSSEL = 0, this register is defined as follows: Description 15:10 Reserved.
Page 446 Gigabit LAN Configuration Registers § § Datasheet...
Page 447: Lpc Interface Pci Register Address Map (Lpc I/F-D31:F0)
LPC Interface Bridge Registers (D31:F0) LPC Interface Bridge Registers (D31:F0) The LPC bridge function of the PCH resides in PCI Device 31:Function 0. This function contains many other functional units, such as DMA and Interrupt controllers, Timers, Power Management, System Management, GPIO, RTC, and LPC Configuration Registers.
Page 448 Size: 16-bit Lockable: Power Well: Core Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 13.1.2 DID—Device Identification Register (LPC I/F—D31:F0) Offset Address: 02h Attribute: – Default Value: See bit description...
Page 449 LPC Interface Bridge Registers (D31:F0) 13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) Offset Address: 04h Attribute: R/W, RO – Default Value: 0007h Size: 16-bit Lockable: Power Well: Core Description 15:10 Reserved Fast Back to Back Enable (FBE) — RO. Hardwired to 0. SERR# Enable (SERR_EN) —...
Page 450 Default Value: See bit description Size: 8 bits Description ® Revision ID (RID) — R/WO. See the Intel 6 Series Chipset Specification Update for the value of the RID Register.. 13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) Offset Address: 09h Attribute:...
Page 451 LPC Interface Bridge Registers (D31:F0) 13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) Offset Address: 0Ah Attribute: Default Value: Size: 8 bits Description Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC bridge. 01h = PCI-to-ISA bridge. 13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0) Offset Address: 0Bh...
Page 452 LPC Interface Bridge Registers (D31:F0) 13.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0) Offset Address: 2Ch Attribute: R/WO – Default Value: 00000000h Size: 32 bits This register is initialized to logic 0 by the assertion of PLTRST#. This register can be written only once after PLTRST# deassertion.
Page 453 LPC Interface Bridge Registers (D31:F0) 13.1.13 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) Offset Address: 44h Attribute: Default Value: Size: 8 bit Lockable: Usage: ACPI, Legacy Power Well: Core Description ACPI Enable (ACPI_EN) — R/W. 0 = Disable. 1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power management function is enabled.
Page 454 LPC Interface Bridge Registers (D31:F0) 13.1.15 GC—GPIO Control Register (LPC I/F — D31:F0) Offset Address: 4Ch Attribute: Default Value: Size: 8 bit Description Reserved. GPIO Enable (EN) — R/W. This bit enables/disables decode of the I/O range pointed to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function. 0 = Disable.
Page 455 LPC Interface Bridge Registers (D31:F0) 13.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register (LPC I/F—D31:F0) Offset Address: PIRQA 60h, PIRQB 61h, Attribute:R/W – – PIRQC 62h, PIRQD – – Default Value: Size:8 bit Lockable: Power Well:Core Description Interrupt Routing Enable (IRQEN) — R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
Page 456 LPC Interface Bridge Registers (D31:F0) 13.1.17 SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0) Offset Address: 64h Attribute: R/W, RO Default Value: Size: 8 bit Lockable: Power Well: Core Description Serial IRQ Enable (SIRQEN) — R/W. 0 = The buffer is input only and internally SERIRQ will be a 1. 1 = Serial IRQs will be recognized.
Page 457 LPC Interface Bridge Registers (D31:F0) 13.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register (LPC I/F—D31:F0) Offset Address: PIRQE 68h, PIRQF 69h, Attribute: – – PIRQG 6Ah, PIRQH – – Default Value: Size: 8 bit Lockable: Power Well: Core Description Interrupt Routing Enable (IRQEN) — R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
Page 458 LPC Interface Bridge Registers (D31:F0) 13.1.20 LPC_HnBDF – HPET n Bus:Device:Function (LPC I/F—D31:F0) Address Offset H0BDF 70h–71h H1BDF 72h–73h H2BDF 74h–75h H3BDF 76h–77h H4BDF 78h–79h H5BDF 7Ah–7Bh H6BDF 7Ch–7Dh H7BDF 7Eh–7Fh Attribute: Default Value: 00F8h Size: 16 bit Description HPET n Bus:Device:Function (HnBDF)— R/W. This field specifies the bus:device:function that the PCH’s HPET n will be using in the following: •...
Page 459 LPC Interface Bridge Registers (D31:F0) 13.1.21 LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—D31:F0) Offset Address: 80h Attribute: Default Value: 0000h Size: 16 bit Description 15:13 Reserved FDD Decode Range — R/W. Determines which range to decode for the FDD Port 0 = 3F0h – 3F5h, 3F7h (Primary) 1 = 370h –...
Page 460 LPC Interface Bridge Registers (D31:F0) 13.1.22 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) Offset Address: 82h Attribute: – Default Value: 0000h Size: 16 bit Power Well: Core Description 15:14 Reserved CNF2_LPC_EN — R/W. Microcontroller Enable # 2. 0 = Disable. 1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used for a microcontroller.
Page 461 LPC Interface Bridge Registers (D31:F0) 13.1.23 GEN1_DEC—LPC I/F Generic Decode Range 1 Register (LPC I/F—D31:F0) Offset Address: 84h Attribute: – Default Value: 00000000h Size: 32 bit Power Well: Core Description 31:24 Reserved Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be 23:18 treated as a match.
Page 462 LPC Interface Bridge Registers (D31:F0) 13.1.25 GEN3_DEC—LPC I/F Generic Decode Range 3 Register (LPC I/F—D31:F0) Offset Address: 8Ch Attribute: – Default Value: 00000000h Size: 32 bit Power Well: Core Description 31:24 Reserved Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be 23:18 treated as a match.
Page 463 LPC Interface Bridge Registers (D31:F0) 13.1.26 GEN4_DEC—LPC I/F Generic Decode Range 4 Register (LPC I/F—D31:F0) Offset Address: 90h Attribute: – Default Value: 00000000h Size: 32 bit Power Well: Core Description 31:24 Reserved Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be 23:18 treated as a match.
Page 464 LPC Interface Bridge Registers (D31:F0) Description SMI Caused by Port 64 Read (TRAPBY64R) — R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 2, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#.
Page 465 LPC Interface Bridge Registers (D31:F0) 13.1.28 LGMR — LPC I/F Generic Memory Range (LPC I/F—D31:F0) Offset Address: 98h Attribute: – Default Value: 00000000h Size: 32 bit Power Well: Core Description Memory Address[31:16] — R/W. This field specifies a 64 KB memory block 31:16 anywhere in the 4 GB memory space that will be decoded to LPC as standard LPC memory cycle if enabled.
Page 466 LPC Interface Bridge Registers (D31:F0) Description BIOS_C8_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC8 0000h – FFCF FFFFh FF88 0000h – FF8F FFFFh BIOS_C0_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC0 0000h –...
Page 467 LPC Interface Bridge Registers (D31:F0) 13.1.31 BIOS_DEC_EN1—BIOS Decode Enable Register (LPC I/F—D31:F0) Offset Address: D8h Attribute: R/W, RO – Default Value: FFCFh Size: 16 bits Description BIOS_F8_EN — RO. This bit enables decoding two 512-KB BIOS memory ranges, and one 128-KB memory range. 0 = Disable 1 = Enable the following ranges for the BIOS FFF80000h –...
Page 468 LPC Interface Bridge Registers (D31:F0) Description BIOS_Legacy_F_EN — R/W. This enables the decoding of the legacy 64KB range at F0000h – FFFFFh. 0 = Disable. 1 = Enable the following legacy ranges for the BIOS F0000h – FFFFFh NOTE: The decode for the BIOS legacy F segment is enabled only by this bit and is not affected by the GEN_PMCON_1.iA64_EN bit.
Page 469 LPC Interface Bridge Registers (D31:F0) 13.1.32 BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) Offset Address: DCh Attribute: R/WLO, R/W, RO Default Value: Size: 8 bit Lockable: Power Well: Core Description Reserved SMM BIOS Write Protect Disable (SMM_BWP)— R/WLO. This bit set defines when the BIOS region can be written by the host. 0 = BIOS region SMM protection is disabled.
Page 470 LPC Interface Bridge Registers (D31:F0) 13.1.33 FDCAP—Feature Detection Capability ID (LPC I/F—D31:F0) Offset Address: E0h–E1h Attribute: Default Value: 0009h Size: 16 bit Power Well: Core Description Next Item Pointer (NEXT) — RO. Configuration offset of the next Capability Item. 15:8 00h indicates the last item in the Capability List.
Page 471 LPC Interface Bridge Registers (D31:F0) 13.1.36 FVECIDX—Feature Vector Index (LPC I/F—D31:F0) Offset Address: E4h–E7h Attribute: Default Value: 00000000h Size: 32 bit Power Well: Core Description 31:6 Reserved Index (IDX) — R/W. 4-bit index pointer into the 64-byte Feature Vector space. Data is read from the FVECD register.
Page 472 See Description Size: 32 bit Power Well: Core Description 31:23 Reserved ® Intel Anti-Theft Technology Capability — RO 0 = Disabled 1 = Capable PCI Express* Ports 7 and 8— RO 0 = Capable 1 = Disabled 20:18 Reserved PCH Integrated Graphics Support Capability — RO...
Page 473 LPC Interface Bridge Registers (D31:F0) 13.1.38.4 FVEC3—Feature Vector Register 3 FVECIDX.IDX: 0011b Attribute: Default Value: See Description Size: 32 bit Power Well: Core Description 31:14 Reserved Data Center Manageability Interface (DCMI) Capability — RO 0 = Capable 1 = Disabled Node Manager Capability —...
Page 474: Dma Registers
LPC Interface Bridge Registers (D31:F0) 13.2 DMA I/O Registers Table 13-2. DMA Registers (Sheet 1 of 2) Port Alias Register Name Default Type Undefined Channel 0 DMA Base & Current Address Undefined Channel 0 DMA Base & Current Count Undefined Channel 1 DMA Base &...
Page 475 LPC Interface Bridge Registers (D31:F0) Table 13-2. DMA Registers (Sheet 2 of 2) Port Alias Register Name Default Type Undefined Channel 7 DMA Base & Current Count Undefined Channel 4–7 DMA Command Undefined Channel 4–7 DMA Status 000001XXb Channel 4–7 DMA Write Single Mask 000000XXb Channel 4–7 DMA Channel Mode Undefined...
Page 476 LPC Interface Bridge Registers (D31:F0) 13.2.2 DMABASE_CC—DMA Base and Current Count Registers I/O Address: Ch. #0 = 01h; Ch. #1 = 03h Attribute: R/W Ch. #2 = 05h; Ch. #3 = 07h Size: 16-bit (per channel), Ch. #5 = C6h; Ch. #6 = CAh but accessed in two 8-bit Ch.
Page 477 LPC Interface Bridge Registers (D31:F0) 13.2.4 DMACMD—DMA Command Register I/O Address: Ch. #0 3 = 08h; – Ch. #4 7 = D0h Attribute: – Default Value: Undefined Size: 8-bit Lockable: Power Well: Core Description Reserved. Must be 0. DMA Group Arbitration Priority — WO. Each channel group is individually assigned either fixed or rotating arbitration priority.
Page 478 LPC Interface Bridge Registers (D31:F0) 13.2.6 DMA_WRSMSK—DMA Write Single Mask Register I/O Address: Ch. #0 3 = 0Ah; – Ch. #4 7 = D4h Attribute: – Default Value: 0000 01xx Size: 8-bit Lockable: Power Well: Core Description Reserved. Must be 0. Channel Mask Select —...
Page 479 LPC Interface Bridge Registers (D31:F0) 13.2.7 DMACH_MODE—DMA Channel Mode Register I/O Address: Ch. #0 3 = 0Bh; – Ch. #4 7 = D6h Attribute: – Default Value: 0000 00xx Size: 8-bit Lockable: Power Well: Core Description DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four different modes: 00 = Demand mode 01 = Single mode...
Page 480 LPC Interface Bridge Registers (D31:F0) 13.2.8 DMA Clear Byte Pointer Register I/O Address: Ch. #0 3 = 0Ch; – Ch. #4 7 = D8h Attribute: – Default Value: xxxx xxxx Size: 8-bit Lockable: Power Well: Core Description Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the I/O port address.
Page 481 LPC Interface Bridge Registers (D31:F0) 13.2.11 DMA_WRMSK—DMA Write All Mask Register I/O Address: Ch. #0 3 = 0Fh; – Ch. #4 7 = DEh Attribute: – Default Value: 0000 1111 Size: 8-bit Lockable: Power Well: Core Description Reserved. Must be 0. Channel Mask Bits —...
Page 482 LPC Interface Bridge Registers (D31:F0) 13.3.1 TCW—Timer Control Word Register I/O Address: Attribute: Default Value: All bits undefined Size: 8 bits This register is programmed prior to any counter being accessed to specify counter modes. Following part reset, the control words for each register are undefined and each counter output is 0.
Page 483 LPC Interface Bridge Registers (D31:F0) RDBK_CMD—Read Back Command The Read Back Command is used to determine the count value, programmed mode, and current states of the OUT pin and Null count flag of the selected counter or counters. Status and/or count may be latched in any or all of the counters by selecting the counter during the register write.
Page 484 LPC Interface Bridge Registers (D31:F0) 13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register I/O Address: Counter 0 = 40h, Counter 1 = 41h, Attribute: Counter 2 = 42h Size: 8 bits per counter Default Value: Bits[6:0] undefined, Bit 7=0 Each counter's status byte can be read following a Read Back Command. If latch status is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte.
Page 485: Pic Registers
LPC Interface Bridge Registers (D31:F0) 13.3.3 Counter Access Ports Register I/O Address: Counter 0 40h, – Counter 1 41h, Attribute: – Counter 2 – Default Value: All bits undefined Size: 8 bit Description Counter Port — R/W. Each counter port address is used to program the 16-bit Count Register.
Page 486 LPC Interface Bridge Registers (D31:F0) 13.4.2 ICW1—Initialization Command Word 1 Register Offset Address: Master Controller Attribute: – Slave Controller Size: 8 bit /controller – Default Value: All bits undefined A write to Initialization Command Word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1.
Page 487 LPC Interface Bridge Registers (D31:F0) 13.4.3 ICW2—Initialization Command Word 2 Register Offset Address: Master Controller Attribute: – Slave Controller Size: 8 bit /controller – Default Value: All bits undefined ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address.
Page 488 0 = This bit should normally be programmed to 0. This is the normal end of interrupt. 1 = Automatic End of Interrupt (AEOI) mode is programmed. Microprocessor Mode — WO. 1 = Must be programmed to 1 to indicate that the controller is operating in an Intel Architecture-based system. Datasheet...
Page 489 LPC Interface Bridge Registers (D31:F0) 13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask) Register Offset Address: Master Controller 021h Attribute:R/W – Slave Controller 0A1h Size: 8 bits – Default Value: Description Interrupt Request Mask — R/W. When a 1 is written to any bit in this register, the corresponding IRQ line is masked.
Page 490 LPC Interface Bridge Registers (D31:F0) 13.4.9 OCW3—Operational Control Word 3 Register Offset Address: Master Controller 020h Attribute: – Slave Controller 0A0h Size: 8 bits – Default Value: Bit[6,0]=0, Bit[7,4:2]=undefined, Bit[5,1]=1 Description Reserved. Must be 0. Special Mask Mode (SMM) — WO. 1 = The Special Mask Mode can be used by an interrupt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits.
Page 491 LPC Interface Bridge Registers (D31:F0) 13.4.10 ELCR1—Master Controller Edge/Level Triggered Register Offset Address: 4D0h Attribute: Default Value: Size: 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode.
Page 492 LPC Interface Bridge Registers (D31:F0) 13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register Offset Address: 4D1h Attribute: Default Value: Size: 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock, IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level mode.
Page 493: Apic Direct Registers
LPC Interface Bridge Registers (D31:F0) 13.5 Advanced Programmable Interrupt Controller (APIC) 13.5.1 APIC Register Map The APIC is accessed using an indirect addressing scheme. Two registers are visible by software for manipulation of most of the APIC registers. These registers are mapped into memory space.
Page 494 LPC Interface Bridge Registers (D31:F0) 13.5.3 DAT—Data Register Memory Address FEC 0000h Attribute: Default Value: 00000000h Size: 32 bits This is a 32-bit register specifying the data to be read or written to the register pointed to by the Index register. This register can only be accessed in DWord quantities. Description APIC Data —...
Page 495 LPC Interface Bridge Registers (D31:F0) 13.5.5 ID—Identification Register Index Offset: Attribute: Default Value: 00000000h Size: 32 bits The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset. Description 31:28 Reserved...
Page 496 LPC Interface Bridge Registers (D31:F0) 13.5.7 REDIR_TBL—Redirection Table Index Offset: 11h (vector 0) throughAttribute: R/W, RO – 3Fh (vector 23) – Default Value: Bit 16 1. All other bits undefinedSize:64 bits each, (accessed as two 32 bit quantities) The Redirection Table has a dedicated entry for each interrupt input pin. The information in the Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin into an APIC message.
Page 497 LPC Interface Bridge Registers (D31:F0) Description Destination Mode — R/W. This field determines the interpretation of the Destination field. 0 = Physical. Destination APIC ID is identified by bits 59:56. 1 = Logical. Destinations are identified by matching bit 63:56 with the Logical Destination in the Destination Format Register and Logical Destination Register in each Local APIC.
Page 498: Rtc I/O Registers
LPC Interface Bridge Registers (D31:F0) 13.6 Real Time Clock Registers 13.6.1 I/O Register Address Map The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the standard and extended banks. The first 14 bytes of the standard bank contain the RTC time and date information along with four registers, A–D, that are used for configuration of the RTC.
Page 499: Rtc (Standard) Ram Bank
LPC Interface Bridge Registers (D31:F0) 13.6.2 Indexed Registers The RTC contains two sets of indexed registers that are accessed using the two separate Index and Target registers (70/71h or 72/73h), as shown in Table 13-7. Table 13-7. RTC (Standard) RAM Bank Index Name Seconds...
Page 500 LPC Interface Bridge Registers (D31:F0) 13.6.2.1 RTC_REGA—Register A RTC Index: Attribute: Default Value: Undefined Size: 8-bit Lockable: Power Well: This register is used for general configuration of the RTC functions. None of the bits are affected by RSMRST# or any other PCH reset signal. Description Update In Progress (UIP) —...
Page 501 LPC Interface Bridge Registers (D31:F0) 13.6.2.2 RTC_REGB—Register B (General Configuration) RTC Index: Attribute: Default Value: U0U00UUU (U: Undefined) Size: 8-bit Lockable: Power Well: Description Update Cycle Inhibit (SET) — R/W. Enables/Inhibits the update cycles. This bit is not affected by RSMRST# nor any other reset signal. 0 = Update cycle occurs normally once each second.
Page 502 LPC Interface Bridge Registers (D31:F0) 13.6.2.3 RTC_REGC—Register C (Flag Register) RTC Index: Attribute: Default Value: 00U00000 (U: Undefined) Size: 8-bit Lockable: Power Well: Writes to Register C have no effect. Description Interrupt Request Flag (IRQF) — RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). This bit also causes the RTC Interrupt to be asserted.
Page 503: Processor Interface Pci Register Address Map
LPC Interface Bridge Registers (D31:F0) 13.7 Processor Interface Registers Table 13-8 is the register address map for the processor interface registers. Table 13-8. Processor Interface PCI Register Address Map Offset Mnemonic Register Name Default Type NMI_SC NMI Status and Control R/W, RO NMI_EN NMI Enable...
Page 504 LPC Interface Bridge Registers (D31:F0) 13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) Register I/O Address: Attribute: R/W (special) Default Value: Size: 8-bit Lockable: Power Well: Core Note: The RTC Index field is write-only for normal operation. This field can only be read in Alt- Access Mode.
Page 505 LPC Interface Bridge Registers (D31:F0) 13.7.5 RST_CNT—Reset Control Register I/O Address: CF9h Attribute: Default Value: Size: 8-bit Lockable: Power Well: Core Description Reserved Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#, SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PWROK going low (with RSMRST# high), or after two TCO timeouts.
Page 506: Power Management Pci Register Address Map (Pm-D31:F0)
LPC Interface Bridge Registers (D31:F0) 13.8 Power Management Registers The power management registers are distributed within the PCI Device 31: Function 0 space, as well as a separate I/O range. Each register is described below. Unless otherwise indicated, bits are in the main (core) power well. Bits not explicitly defined in each register are assumed to be reserved.
Page 507 LPC Interface Bridge Registers (D31:F0) 13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0) Offset Address: A0h Attribute: R/W, RO, R/WO Default Value: 0000h Size: 16-bit Lockable: Usage: ACPI, Legacy Power Well: Core Description 15:11 Reserved BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated with the PCI Express* ports.
Page 508 LPC Interface Bridge Registers (D31:F0) 13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0) Offset Address: A2h Attribute: R/W, RO, R/WC Default Value: Size: 8-bit Lockable: Usage: ACPI, Legacy Power Well: Resume Description DRAM Initialization Bit — R/W. This bit does not affect hardware functionality in any way.
Page 509 LPC Interface Bridge Registers (D31:F0) Description SYS_PWROK Failure (SYSPWR_FLR) — R/WC. 0 = This bit will be cleared only be software writing a 1 back to the bit or by SUS well power loss. 1 = This bit will be set any time SYS_PWROK drops unexpectedly when the system was in S0 or S1 state.
Page 510 SLP_LAN# Default Value (SLP_LAN_DEFAULT) — R/W. This bit specifies the value to drive on the SLP_LAN# pin when in Sx/Moff and Intel ME FW nor host BIOS has configured SLP_LAN#. When this bit is set to 1 SLP_LAN# will default to be driven high, when set to 0 SLP_LAN# will default to be driven low.
Page 511 LPC Interface Bridge Registers (D31:F0) Description SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum assertion width of the SLP_S4# signal to ensure that the DRAM modules have been safely power-cycled. Valid values are: 11 = 1 second 10 = 2 seconds 01 = 3 seconds 00 = 4 seconds...
Page 512 LPC Interface Bridge Registers (D31:F0) 13.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration Lock Register Offset Address: A6h Attribute: RO, R/WLO Default Value: Size: 8-bit Lockable: Usage: ACPI Power Well: Core Description Reserved SLP Stretching Policy Lock-Down (SLP_STR_POL_LOCK) — R/WLO. When set to 1, this bit locks down the Disable SLP Stretching After SUS Well Power Up, SLP_S3# Minimum Assertion Width, SLP_S4# Minimum Assertion Width, SLP_S4# Assertion Stretch Enable bits in the GEN_PMCON_3 register, making them read- only.
Page 513 1 = EHCI traffic will cause BM_STS to be set. Reserved HDA_BREAK_EN — R/W. ® 0 = Intel High Definition Audio traffic will not cause BM_STS to be set. ® 1 = Intel High Definition Audio traffic will cause BM_STS to be set.
Page 514 ® When set, a CF9h write of 6h or Eh will cause a Global reset of both the Host and Intel ME partitions. If this bit is cleared, a CF9h write of 6h or Eh will only reset the host partition.
Page 515: Apm Register Map
LPC Interface Bridge Registers (D31:F0) 13.8.2 APM I/O Decode Table 13-10 shows the I/O registers associated with APM support. This register space is enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location). Table 13-10.
Page 516: Acpi And Legacy I/O Register Map
LPC Interface Bridge Registers (D31:F0) 13.8.3 Power Management I/O Registers Table 13-11 shows the registers associated with ACPI and Legacy power management support. These registers locations are all offsets from the ACPI base address defined in the PCI Device 31: Function 0 space (PMBASE), and can be moved to any 128-byte aligned I/O location.
Page 517 LPC Interface Bridge Registers (D31:F0) 13.8.3.1 PM1_STS—Power Management 1 Status Register I/O Address: PMBASE + 00h Attribute: R/WC Default Value: 0000h Size: 16-bit Lockable: Usage: ACPI or Legacy Power Well: Bits 0 7: Core, – Bits 12-15: Resume Bit 11: RTC, Bits 8 and 10: DSW If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN register, then the PCH will generate a Wake Event.
Page 518 1 = This bit is set any time a Power Button Override occurs (that is, the power button is pressed for at least 4 consecutive seconds), due to the corresponding bit in the SMBus slave message, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down or due to an internal thermal sensor catastrophic condition.
Page 519 In addition to being cleared by RTCRST# assertion, the PCH also clears this bit due to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, processor thermal trip event, or due to an internal thermal sensor catastrophic condition.
Page 520 LPC Interface Bridge Registers (D31:F0) 13.8.3.3 PM1_CNT—Power Management 1 Control I/O Address: PMBASE + 04h Attribute: R/W, WO Default Value: 00000000h Size: 32-bit Lockable: Usage: ACPI or Legacy Power Well: Bits 0 7: Core, – Bits 8 12: RTC, – Bits 13 15: Resume –...
Page 521 LPC Interface Bridge Registers (D31:F0) 13.8.3.4 PM1_TMR—Power Management 1 Timer Register I/O Address: PMBASE + 08h Attribute: Default Value: xx000000h Size: 32-bit Lockable: Usage: ACPI Power Well: Core Description 31:24 Reserved Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4).
Page 522 LPC Interface Bridge Registers (D31:F0) 13.8.3.5 GPE0_STS—General Purpose Event 0 Status Register I/O Address: PMBASE + 20h Attribute: Bits 0:32,35 R/WC Bits 33:34, 36:63 RO Default Value: 0000000000000000h Size: 64-bit Lockable: Usage: ACPI Power Well: Resume, Bits 0–34, 56–63: Bit 35: DSW This register is symmetrical to the General Purpose Event 0 Enable Register.
Page 523 The default for this bit is 0. Writing a 1 to this bit position clears this bit. The following are internal devices which can set this bit: • Intel HD Audio • Intel Management Engine “maskable” wake events • Integrated LAN • SATA •...
Page 524 LPC Interface Bridge Registers (D31:F0) Description RI_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RI# input signal goes active. SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can independently cause an SMI# or SCI, so this bit does not need to do so (unlike the other bits in this register).
Page 525 NOTE: Enables the setting of the PME_B0_STS bit to generate a wake event and/or an SCI or SMI#. In addition to being cleared by RTCRST# assertion, the PCH also clears this bit due to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, processor thermal trip event, or due to an internal thermal sensor catastrophic condition.
Page 526 In addition to being cleared by RTCRST# assertion, the PCH also clears this bit due Only) to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, processor thermal trip event, or due to an internal thermal sensor catastrophic condition.
Page 527 Once written to 1, this bit can only be cleared by PLTRST#. 26:19 Reserved INTEL_USB2_EN — R/W. 0 = Disable 1 = Enables Intel-Specific EHCI SMI logic to cause SMI#. LEGACY_USB2_EN — R/W. 0 = Disable 1 = Enables legacy EHCI logic to cause SMI#. 16:15 Reserved PERIODIC_EN —...
Page 528 LPC Interface Bridge Registers (D31:F0) Description Software SMI# Timer Enable (SWSMI_TMR_EN) — R/W. 0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the SMI# will not be generated. 1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated.
Page 529 INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits in the Intel-Specific EHCI SMI Status Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set.
Page 530 LPC Interface Bridge Registers (D31:F0) Description SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by writing a 1 to it. 0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must wait at least 15.63 s after the initial assertion of this bit before clearing it.
Page 531 LPC Interface Bridge Registers (D31:F0) Description Reserved SWSMI_TMR_STS — R/WC. Software clears this bit by writing a 1 to it. 0 = Software SMI# Timer has Not expired. 1 = Set by the hardware when the Software SMI# Timer expires. APM_STS —...
Page 532 In addition to being cleared by RSMRST# assertion, the PCH also clears this bit due to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, processor thermal trip event, or due to an internal thermal sensor catastrophic condition.
Page 533 LPC Interface Bridge Registers (D31:F0) 13.8.3.12 DEVACT_STS — Device Activity Status Register I/O Address: PMBASE +44h Attribute: R/WC Default Value: 0000h Size: 16-bit Lockable: Usage: Legacy Only Power Well: Core Each bit indicates if an access has occurred to the corresponding device’s trap range, or for bits 6:9 if the corresponding PCI interrupt is active.
Page 534: Tco I/O Register Address Map
LPC Interface Bridge Registers (D31:F0) 13.9 System Management TCO Registers The TCO logic is accessed using registers mapped to the PCI configuration space (Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers, see LPC Device 31:Function 0 PCI Configuration registers. TCO Register I/O Map The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which is, PMBASE + 60h in the PCI config space.
Page 535 LPC Interface Bridge Registers (D31:F0) 13.9.2 TCO_DAT_IN—TCO Data In Register I/O Address: TCOBASE +02h Attribute: Default Value: Size: 8-bit Lockable: Power Well: Core Description TCO Data In Value — R/W. This data register field is used for passing commands from the OS to the SMI handler.
Page 536 LPC Interface Bridge Registers (D31:F0) Description BIOSWR_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = PCH sets this bit and generates and SMI# to indicate an invalid attempt to write to the BIOS. This occurs when either: a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or b) any write is attempted to the BIOS and the BIOSWP bit is also set.
Page 537 LPC Interface Bridge Registers (D31:F0) 13.9.5 TCO2_STS—TCO2 Status Register I/O Address: TCOBASE +06h Attribute: R/WC Default Value: 0000h Size: 16-bit Lockable: Power Well: Resume (Except Bit 0, in RTC) Description 15:5 Reserved SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) — R/WC. Allow the software to go directly into a pre-determined sleep state.
Page 538 LPC Interface Bridge Registers (D31:F0) 13.9.6 TCO1_CNT—TCO1 Control Register I/O Address: TCOBASE +08h Attribute: R/W, R/WLO, R/WC Default Value: 0000h Size: 16-bit Lockable: Power Well: Core Description 15:13 Reserved TCO_LOCK — R/WLO. When set to 1, this bit prevents writes from changing the TCO_EN bit (in offset 30h of Power Management I/O space).
Page 539 LPC Interface Bridge Registers (D31:F0) 13.9.7 TCO2_CNT—TCO2 Control Register I/O Address: TCOBASE +0Ah Attribute: Default Value: 0008h Size: 16-bit Lockable: Power Well: Resume Description 15:6 Reserved OS_POLICY — R/W. OS-based software writes to these bits to select the policy that the BIOS will use after the platform resets due the WDT.
Page 540 LPC Interface Bridge Registers (D31:F0) 13.9.9 TCO_WDCNT—TCO Watchdog Control Register Offset Address: TCOBASE + 0Eh Attribute: Default Value: Size: 8 bits Power Well: Resume Description The BIOS or system management software can write into this register to indicate more details on the boot progress. The register will reset to 00h based on a RSMRST# (but not PLTRST#).
Page 541: Registers To Control Gpio Address Map
LPC Interface Bridge Registers (D31:F0) 13.10 General Purpose I/O Registers The control for the general purpose I/O signals is handled through a 128-byte I/O space. The base offset for this space is selected by the GPIOBASE register. Table 13-13. Registers to Control GPIO Address Map GPIOBASE Mnemonic Register Name...
Page 542 LPC Interface Bridge Registers (D31:F0) 13.10.1 GPIO_USE_SEL—GPIO Use Select Register Offset Address: GPIOBASE + 00h Attribute: Default Value: B96BA1FFh Size: 32-bit Lockable: Power Well: Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GPIO_USE_SEL[31:0] — R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function.
Page 543 The value reported in this register is undefined when programmed as native mode. NOTE: Bit 29 setting will be ignored if Intel ME FW is configuring SLP_LAN# behavior. When GPIO29/SLP_LAN# Select Soft-strap is set to 1 (GPIO usage), bit 29 can be used as regular GP_LVL bit.
Page 544 LPC Interface Bridge Registers (D31:F0) 13.10.5 GP_SER_BLINK—GP Serial Blink Offset Address: GPIOBASE +1Ch Attribute: Default Value: 00000000h Size: 32-bit Lockable: Power Well: Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GP_SER_BLINK[31:0] — R/W. The setting of this bit has no effect if the corresponding GPIO is programmed as an input or if the corresponding GPIO has the GPO_BLINK bit set.
Page 545 LPC Interface Bridge Registers (D31:F0) 13.10.7 GP_SB_DATA—GP Serial Blink Data Offset Address: GPIOBASE +24h Attribute: Default Value: 00000000h Size: 32-bit Lockable: Power Well: Core Description GP_SB_DATA[31:0] — R/W. This register contains the data serialized out. The 31:0 number of bits shifted out are selected through the DLS field in the GP_SB_CMDSTS register.
Page 546 LPC Interface Bridge Registers (D31:F0) 13.10.10 GPI_INV—GPIO Signal Invert Register Offset Address: GPIOBASE +2Ch Attribute: Default Value: 00000000h Size: 32-bit Lockable: Power Well: Core for 17, 16, 7:0 Description 31:16 Reserved Input Inversion (GP_INV[n]) — R/W. This bit only has effect if the corresponding GPIO is used as an input and used by the GPE logic, where the polarity matters.
Page 547 LPC Interface Bridge Registers (D31:F0) 13.10.12 GP_IO_SEL2—GPIO Input/Output Select 2 Register Offset Address: GPIOBASE +34h Attribute: Default Value: 1F57FFF4h Lockable: Power Well: Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GP_IO_SEL2[63:32] — R/W. 0 = GPIO signal is programmed as an output. 31:0 1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is programmed as an input.
Page 548 LPC Interface Bridge Registers (D31:F0) 13.10.14 GPIO_USE_SEL3—GPIO Use Select 3 Register Offset Address: GPIOBASE +40h Attribute: Default Value: 00000130h (Desktop) Size: 32-bit 00000030h (Mobile) Lockable: Power Well: Core for 0:7, 16:23, Resume for 8:15, 24:31 Description 31:12 Always 0. No corresponding GPIO. GPIO_USE_SEL3[75:64]—...
Page 549 LPC Interface Bridge Registers (D31:F0) 13.10.16 GP_LVL3—GPIO Level for Input or Output 3 Register Offset Address: GPIOBASE +48h Attribute: Default Value: 000000C0h Size: 32-bit Lockable: Power Well: Core for 0:7, 16:23, Resume for 8:15, 24:31 Description 31:12 Always 0. No corresponding GPIO. GP_LVL[75:72]—...
Page 550 LPC Interface Bridge Registers (D31:F0) 13.10.18 GP_RST_SEL2 — GPIO Reset Select Offset Address: GPIOBASE +64h Attribute: Default Value: 00000000h Size: 32-bit Lockable: Power Well: Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GP_RST_SEL[63:56] — R/W. 0 = Corresponding GPIO registers will be reset by PWROK deassertion, CF9h reset (06h 31:24 or 0Eh), or SYS_RESET# assertion.
Page 551: Sata Controller Pci Register Address Map (Sata-D31:F2)
SATA Controller Registers (D31:F2) SATA Controller Registers (D31:F2) 14.1 PCI Configuration Registers (SATA–D31:F2) Note: Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 14-1.
Page 552 SATA Controller Registers (D31:F2) Table 14-1. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 2 of 2) Offset Mnemonic Register Name Default Type 42h–43h IDE_TIM Secondary IDE Timing Register 0000h See register 70h–71h PCI Power Management Capability ID description See register 72h–73h PCI Power Management Capabilities description...
Page 553 Size: 16 bit Lockable: Power Well: Core Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 14.1.2 DID—Device Identification Register (SATA—D31:F2) Offset Address: 02h Attribute: – Default Value: See bit description...
Page 554 SATA Controller Registers (D31:F2) 14.1.4 PCISTS — PCI Status Register (SATA–D31:F2) Address Offset: 06h Attribute: R/WC, RO – Default Value: 02B0h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect.
Page 555: When Sub Class Code Register (D31:F2:Offset 0Ah) = 01H
Default Value: See bit description Size: 8 bits Description ® Revision ID — RO. See the Intel 6 Series Chipset Specification Update for the value of the RID Register. 14.1.6 PI—Programming Interface Register (SATA–D31:F2) 14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h...
Page 556 SATA Controller Registers (D31:F2) 14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h Address Offset: 09h Attribute: Default Value: Size: 8 bits Description Interface (IF) — RO. When configured as RAID, this register becomes read only 0. 14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h Address Offset: 09h Attribute: Default Value:...
Page 557 SATA Controller Registers (D31:F2) 14.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2) Address Offset: 0Dh Attribute: Default Value: Size: 8 bits Description Master Latency Timer Count (MLTC) — RO. 00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer.
Page 558 SATA Controller Registers (D31:F2) 14.1.12 PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F2) Address Offset: 14h Attribute: R/W, RO – Default Value: 00000001h Size: 32 bits Description 31:16 Reserved Base Address — R/W. This field provides the base address of the I/O space (4 15:2 consecutive I/O locations).
Page 559 SATA Controller Registers (D31:F2) 14.1.15 BAR—Legacy Bus Master Base Address Register (SATA–D31:F2) Address Offset: 20h Attribute: R/W, RO – Default Value: 00000001h Size: 32 bits The Bus Master IDE interface function uses Base Address register 5 to request a 16- byte I/O space to provide a software interface to the Bus Master functions.
Page 560 SATA Controller Registers (D31:F2) 14.1.16.2 When SCC is 01h When the programming interface is IDE, the register becomes an I/O BAR allocating 16 bytes of I/O space for the I/O-mapped registers defined in Section 14.2. Note that although 16 bytes of locations are allocated, only 8 bytes are used as SINDX and SDATA registers;...
Page 561 SATA Controller Registers (D31:F2) 14.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) Address Offset: 3Ch Attribute: Default Value: Size: 8 bits Function Level Reset:No Description Interrupt Line — R/W. This field is used to communicate to software the interrupt line that the interrupt pin is connected to. Interrupt Line register is not reset by FLR.
Page 562 SATA Controller Registers (D31:F2) 14.1.24 PC—PCI Power Management Capabilities Register (SATA–D31:F2) Address Offset: 72h Attribute: – Default Value: See Register Description Size: 16 bits Bits Description PME Support (PME_SUP) — RO. 00000 = If SCC = 01h, indicates no PME support in IDE mode. 15:11 01000 = If SCC is not 01h, in a non-IDE mode, indicates PME# can be generated from the D3...
Page 563 SATA Controller Registers (D31:F2) 14.1.25 PMCS—PCI Power Management Control and Status Register (SATA–D31:F2) Address Offset: 74h Attribute: R/W, R/WC – Default Value: 0008h Size: 16 bits Function Level Reset: No (Bits 8 and 15) Bits Description PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if this bit and PMEE is set, a PME# will be generated from the SATA controller NOTE: Whenever SCC = 01h, hardware will automatically change the attribute of this bit to RO 0.
Page 564 SATA Controller Registers (D31:F2) 14.1.26 MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) Address Offset: 80h Attribute: – Default Value: 7005h Size: 16 bits Note: There is no support for MSI when the software is operating in legacy (IDE) mode when AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make sure that MSI is disabled.
Page 565 SATA Controller Registers (D31:F2) Bits Description Multiple Message Enable (MME) — RO. = 000 (and MSIE is set), a single MSI message will be generated for all SATA ports, and bits [15:0] of the message vector will be driven from MD[15:0]. For 6 port components: Value Driven on MSI Memory Write Bits[15:3]...
Page 566 SATA Controller Registers (D31:F2) 14.1.28 MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2) Address Offset: 84h Attribute: – Default Value: 00000000h Size: 32 bits Note: There is no support for MSI when the software is operating in legacy (IDE) mode when AHCI is not enabled.
Page 567 SATA Controller Registers (D31:F2) 14.1.30 MAP—Address Map Register (SATA–D31:F2) Address Offset: 90h Attribute: R/W, R/WO Default Value: 0000h Size: 16 bits Function Level Reset: No (Bits 7:5 and 13:8 only) Bits Description 15:8 Reserved SATA Mode Select (SMS) — R/W. Software programs these bits to control the mode in which the SATA Controller should operate: 00b = IDE mode 01b = AHCI mode...
Page 568 SATA Controller Registers (D31:F2) 14.1.31 PCS—Port Control and Status Register (SATA–D31:F2) Address Offset: 92h Attribute: R/W, RO – Default Value: 0000h Size: 16 bits Function Level Reset: No By default, the SATA ports are set to the disabled state (bits [5:0] = 0). When enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices.
Page 569 SATA Controller Registers (D31:F2) Bits Description Port 1 Present (P1P) — RO. The status of this bit may change at any time. This bit is cleared when the port is disabled using P1E. This bit is not cleared upon surprise removal of a device.
Page 570 SATA Controller Registers (D31:F2) Bits Description Port 0 Enabled (P0E) — R/W / RO. 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices.
Page 571 Device ID 1C04h for Desktop or 1C05h for Mobile to (RAID ® prevent the Microsoft Windows Vista in-box version of the Intel Rapid Capable Storage Manager from loading on the platform and will require the user to SKUs ®...
Page 572 SATA Controller Registers (D31:F2) 14.1.34 SATACR0—SATA Capability Register 0 (SATA–D31:F2) Address Offset: A8h–ABh Attribute: RO, R/WO Default Value: 0010B012h Size: 32 bits Function Level Reset: No (Bits 15:8 only) Note: This register is read-only 0 when SCC is 01h. Description 31:24 Reserved Major Revision (MAJREV) —...
Page 573 SATA Controller Registers (D31:F2) 14.1.36 FLRCID—FLR Capability ID (SATA–D31:F2) Address Offset: B0–B1h Attribute: Default Value: 0009h Size: 16 bits Description 15:8 Next Capability Pointer — RO. 00h indicates the final item in the capability list. Capability ID — RO. The value of this field depends on the FLRCSSEL (RCBA+3410h:bit 12) bit.
Page 574 SATA Controller Registers (D31:F2) 14.1.38 FLRC—FLR Control (SATA–D31:F2) Address Offset: B4–B5h Attribute: RO, R/W Default Value: 0000h Size: 16 bits Description 15:9 Reserved. Transactions Pending (TXP) — RO. 0 = Controller has received all non-posted requests. 1 = Controller has issued non-posted requests which has not been completed. Reserved.
Page 575 SATA Controller Registers (D31:F2) 14.1.40 ATS—APM Trapping Status Register (SATA–D31:F2) Address Offset: C4h Attribute: R/WC Default Value: Size: 8 bits Function Level Reset:No Description Reserved Secondary Slave Trap (SST) — R/WC. Indicates that a trap occurred to the secondary slave device. Secondary Master Trap (SPT) —...
Page 576 SATA Controller Registers (D31:F2) 14.1.42 BFCS—BIST FIS Control/Status Register (SATA–D31:F2) Address Offset: E0h Attribute: R/W, R/WC – Default Value: 00000000h Size: 32 bits Bits Description 31:16 Reserved Port 5 BIST FIS Initiate (P5BFI) — R/W. When a rising edge is detected on this bit field, the PCH initiates a BIST FIS to the device on Port 5, using the parameters specified in this register and the data specified in BFTD1 and BFTD2.
Page 577 SATA Controller Registers (D31:F2) Bits Description BIST FIS Successful (BFS) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a BIST FIS transmitted by PCH receives an R_OK completion status from the device.
Page 578 SATA Controller Registers (D31:F2) 14.1.43 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) Address Offset: E4h Attribute: – Default Value: 00000000h Size: 32 bits Bits Description BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form the contents of the second DWord of any BIST FIS initiated by the PCH. This register is not port specific—its contents will be used for BIST FIS initiated on any port.
Page 579: Bus Master Ide I/O Register Address Map
SATA Controller Registers (D31:F2) 14.2 Bus Master IDE I/O Registers (D31:F2) The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR register, located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted).
Page 580 SATA Controller Registers (D31:F2) 14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) Address Offset: Primary: BAR + 00h Attribute: Secondary: BAR + 08h Default Value: Size: 8 bits Description Reserved. Returns 0. Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master transfer.
Page 581 SATA Controller Registers (D31:F2) 14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO Secondary: BAR + 0Ah Default Value: Size: 8 bits Description Simplex Only — RO. 0 = Both bus master channels (primary and secondary) can be operated independently and can be used at the same time.
Page 582 SATA Controller Registers (D31:F2) 14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2) Address Offset: Primary: BAR + 04h–07h Attribute: Secondary: BAR + 0Ch – Default Value: All bits undefined Size: 32 bits Description Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits [31:2] of the memory location of the Physical Region Descriptor (PRD).
Page 583 SATA Controller Registers (D31:F2) 14.3 Serial ATA Index/Data Pair Superset Registers All of these I/O registers are in the core well. They are exposed only when SCC is 01h (that is, IDE programming interface). These are Index/Data Pair registers that are used to access the SerialATA superset registers (SerialATA Status (PxSSTS), SerialATA Control (PxSCTL) and SerialATA Error (PxSERR)).
Page 584 SATA Controller Registers (D31:F2) 14.3.2 SDATA—Serial ATA Data (D31:F2) Address Offset: SIDPBA + 04h Attribute: Default Value: 00000000h Size: 32 bits Description Data (DATA)—R/W. This Data register is a “window” through which data is read or written to from the register pointed to by the Serial ATA Index (SINDX) register above. Note that a physical register is not actually implemented as the data is actually stored 31:0 in the memory mapped registers.
Page 585 SATA Controller Registers (D31:F2) Description Device Detection (DET) — RO. Indicates the interface device detection and Phy state: Value Description No device detected and Phy communication not established Device presence detected but Phy communication not established Device presence detected and Phy communication established Phy in offline mode as a result of the interface being disabled or running in a BIST loopback mode All other values reserved.
Page 586 SATA Controller Registers (D31:F2) Description Device Detection Initialization (DET) — R/W. Controls the PCH’s device detection and interface initialization. Value Description No device detection or initialization action requested Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications re- initialized Disable the Serial ATA interface and put Phy in offline mode...
Page 587 SATA Controller Registers (D31:F2) Description 10b to 8b Decode Error (B). Indicates that one or more 10b to 8b decoding errors occurred. Comm Wake (W). Indicates that a Comm Wake signal was detected by the Phy. Phy Internal Error (I). Indicates that the Phy detected some internal error. PhyRdy Change (N): When set to 1, this bit indicates that the internal PhyRdy signal changed state since the last time this bit was cleared.
Page 588: Ahci Register Address Map
SATA Controller Registers (D31:F2) 14.4 AHCI Registers (D31:F2) Note: These registers are AHCI-specific and available when the PCH is properly configured. The Serial ATA Status, Control, and Error registers are special exceptions and may be accessed on all PCH components if properly configured; see Section 14.3 for details.
Page 589: Generic Host Controller Register Address Map
Command Completion Coalescing 18h–1Bh CCC_PORTS 00000000h Ports 1Ch–1Fh EM_LOC Enclosure Management Location 01600002h R/W, R/WO, 20h–23h EM_CTRL Enclosure Management Control 07010000h 70h–73h AHCI Version 00010000h A0h–A3h Vendor Specific 00000001h RO, R/WO ® C8h–C9h RSTF Intel RST Feature Capabilities 003Fh R/WO Datasheet...
Page 590 SATA Controller Registers (D31:F2) 14.4.1.1 CAP—Host Capabilities Register (D31:F2) Address Offset: ABAR + 00h–03h Attribute: R/WO, RO Default Value: FF22FFC2h (Desktop) Size: 32 bits DE127F03h (Mobile) Function Level Reset:No All bits in this register that are R/WO are reset only by PLTRST#. Description Supports 64-bit Addressing (S64A) —...
Page 591 SATA Controller Registers (D31:F2) Description Supports AHCI Mode Only (SAM) — RO. The SATA controller may optionally support AHCI access mechanism only. 0 = SATA controller supports both IDE and AHCI Modes 1 = SATA controller supports AHCI Mode Only Supports Port Multiplier (PMS) —...
Page 592 SATA Controller Registers (D31:F2) 14.4.1.2 GHC—Global PCH Control Register (D31:F2) Address Offset: ABAR + 04h–07h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits Description AHCI Enable (AE) — R/W. When set, this bit indicates that an AHCI driver is loaded and the controller will be talked to using AHCI mechanisms.
Page 593 SATA Controller Registers (D31:F2) 14.4.1.3 IS—Interrupt Status Register (D31:F2) Address Offset: ABAR + 08h Attribute: R/WC – Default Value: 00000000h Size: 32 bits This register indicates which of the ports within the controller have an interrupt pending and require service. Description 31:6 Reserved.
Page 594 SATA Controller Registers (D31:F2) 14.4.1.4 PI—Ports Implemented Register (D31:F2) Address Offset: ABAR + 0Ch–0Fh Attribute: R/WO, RO Default Value: 00000000h Size: 32 bits Function Level Reset:No This register indicates which ports are exposed to the PCH. It is loaded by platform BIOS.
Page 595 SATA Controller Registers (D31:F2) 14.4.1.5 VS—AHCI Version (D31:F2) Address Offset: ABAR + 10h–13h Attribute: Default Value: 00010300h Size: 32 bits This register indicates the major and minor version of the AHCI specification. It is BCD encoded. The upper two bytes represent the major version number, and the lower two bytes represent the minor version number.
Page 596 SATA Controller Registers (D31:F2) 14.4.1.7 EM_CTRL—Enclosure Management Control Register (D31:F2) Address Offset: ABAR + 20h–23h Attribute: R/W, R/WO, RO Default Value: 07010000h Size: 32 bits This register is used to control and obtain status for the enclosure management interface. This register includes information on the attributes of the implementation, enclosure management messages supported, the status of the interface, whether any message are pending, and is used to initiate sending messages.
Page 597 SATA Controller Registers (D31:F2) 14.4.1.8 CAP2—HBA Capabilities Extended Address Offset: ABAR + 24h–27h Attribute: Default Value: 00000004h Size: 32 bits Function Level Reset:No Description 31:3 Reserved Automatic Partial to Slumber Transitions (APST) 0= Not supported 1= Supported Reserved 14.4.1.9 VSP—Vendor Specific (D31:F2) Address Offset: ABAR + A0h–A3h Attribute: RO, R/WO...
Page 598 Intel RRT Only on eSATA (IROES) —R/WO ® When set to 1, indicates that only Intel Rapid Recovery Technology (RRT) volumes can span internal and external SATA (eSATA). If not set, any RAID volume can span internal and external SATA.
Page 599: Port [5:0] Dma Register Address Map
SATA Controller Registers (D31:F2) 14.4.2 Port Registers (D31:F2) Ports not available will result in the corresponding Port DMA register space being reserved. The controller shall ignore writes to the reserved space on write cycles and shall return 0 on read cycle accesses to the reserved location. Table 14-5.
Page 600 SATA Controller Registers (D31:F2) Table 14-5. Port [5:0] DMA Register Address Map (Sheet 2 of 3) ABAR + Mnemonic Register Offset Registers may be Reserved depending on if port is available in 200h–27Fh — the given SKU. See Section 1.3 for details if port is available.
Page 601 SATA Controller Registers (D31:F2) Table 14-5. Port [5:0] DMA Register Address Map (Sheet 3 of 3) ABAR + Mnemonic Register Offset 308h–30Bh P4FB Port 4 FIS Base Address 30Ch–30Fh P4FBU Port 4 FIS Base Address Upper 32-Bits 310h–313h P4IS Port 4 Interrupt Status 314h–317h P4IE Port 4 Interrupt Enable...
Page 602 SATA Controller Registers (D31:F2) 14.4.2.1 PxCLB—Port [5:0] Command List Base Address Register (D31:F2) Address Offset: Port 0: ABAR + 100h Attribute: Port 1: ABAR + 180h Port 2: ABAR + 200h (if port available; see Section 1.3) Port 3: ABAR + 280h (if port available; see Section 1.3) Port 4: ABAR + 300h...
Page 603 SATA Controller Registers (D31:F2) 14.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2) Address Offset: Port 0: ABAR + 108h Attribute: Port 1: ABAR + 188h Port 2: ABAR + 208h (if port available; see Section 1.3) Port 3: ABAR + 288h (if port available; see Section 1.3) Port 4: ABAR + 308h...
Page 604 SATA Controller Registers (D31:F2) 14.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2) Address Offset: Port 0: ABAR + 110h Attribute: R/WC, RO Port 1: ABAR + 190h Port 2: ABAR + 210h (if port available; see Section 1.3) Port 3: ABAR + 290h (if port available; see Section 1.3) Port 4: ABAR + 310h...
Page 605 SATA Controller Registers (D31:F2) Description Unknown FIS Interrupt (UFS) — RO. When set to 1, this bit indicates that an unknown FIS was received and has been copied into system memory. This bit is cleared to 0 by software clearing the PxSERR.DIAG.F bit to 0. Note that this bit does not directly reflect the PxSERR.DIAG.F bit.
Page 606 SATA Controller Registers (D31:F2) Description Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and PxIS.IPMS are set, the PCH will generate an interrupt. NOTE: FIS based Port Multipliers only supported on SATA ports 4 and 5 by PCH PhyRdy Change Interrupt Enable (PRCE) —...
Page 607 SATA Controller Registers (D31:F2) 14.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2) Address Offset: Port 0: ABAR + 118h Attribute: R/W, RO, R/WO Port 1: ABAR + 198h Port 2: ABAR + 218h (if port available; see Section 1.3) Port 3: ABAR + 298h (if port available; see Section 1.3) Port 4: ABAR + 318h...
Page 608 SATA Controller Registers (D31:F2) Description Drive LED on ATAPI Enable (DLAE) — R/W. When set to 1, the PCH will drive the LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA commands. When cleared, the PCH will only drive the LED pin active for ATA commands.
Page 609 SATA Controller Registers (D31:F2) Description Current Command Slot (CCS) — RO. Indicates the current command slot the PCH is processing. This field is valid when the ST bit is set in this register, and is constantly updated by the PCH. This field can be updated as soon as the PCH recognizes an active command slot, or at some point soon after when it begins processing the command.
Page 610 SATA Controller Registers (D31:F2) 14.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2) Address Offset: Port 0: ABAR + 120h Attribute: Port 1: ABAR + 1A0h Port 2: ABAR + 220h (if port available; see Section 1.3) Port 3: ABAR + 2A0h (if port available; see Section 1.3) Port 4: ABAR + 320h...
Page 611 SATA Controller Registers (D31:F2) 14.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) Address Offset: Port 0: ABAR + 128h Attribute: Port 1: ABAR + 1A8h Port 2: ABAR + 228h (if port available; see Section 1.3) Port 3: ABAR + 2A8h (if port available; see Section 1.3) Port 4: ABAR + 328h...
Page 612 SATA Controller Registers (D31:F2) 14.4.2.11 PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2) Address Offset: Port 0: ABAR + 12Ch Attribute: R/W, RO Port 1: ABAR + 1ACh Port 2: ABAR + 22Ch (if port available; see Section 1.3) Port 3: ABAR + 2ACh (if port available;...
Page 613 SATA Controller Registers (D31:F2) Description Device Detection Initialization (DET) — R/W. Controls the PCH’s device detection and interface initialization. Value Description No device detection or initialization action requested Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications re-initialized Disable the Serial ATA interface and put Phy in offline mode...
Page 614 SATA Controller Registers (D31:F2) Description CRC Error (C) — R/WC. Indicates that one or more CRC errors occurred with the Link Layer. Disparity Error (D) — R/WC. This field is not used by AHCI. 10b to 8b Decode Error (B) — R/WC. Indicates that one or more 10b to 8b decoding errors occurred.
Page 615 SATA Controller Registers (D31:F2) 14.4.2.13 PxSACT—Port [5:0] Serial ATA Active (D31:F2) Address Offset: Port 0: ABAR + 134h Attribute: Port 1: ABAR + 1B4h Port 2: ABAR + 234h (if port available; see Section 1.3) Port 3: ABAR + 2B4h (if port available; see Section 1.3) Port 4: ABAR + 334h...
Page 616 SATA Controller Registers (D31:F2) Datasheet...
Page 617: Sata Controller Pci Register Address Map (Sata-D31:F5)
SATA Controller Registers (D31:F5) SATA Controller Registers (D31:F5) 15.1 PCI Configuration Registers (SATA–D31:F5) Note: Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 15-1.
Page 618 Size: 16 bit Lockable: Power Well: Core Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 15.1.2 DID—Device Identification Register (SATA—D31:F5) Offset Address: 02h Attribute: – Default Value: See bit description...
Page 619 SATA Controller Registers (D31:F5) 15.1.3 PCICMD—PCI Command Register (SATA–D31:F5) Address Offset: 04h Attribute: RO, R/W – Default Value: 0000h Size: 16 bits Description 15:11 Reserved Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled.
Page 620 Reserved 15.1.5 RID—Revision Identification Register (SATA—D31:F5) Offset Address: 08h Attribute: Default Value: See bit description Size: 8 bits Description ® Revision ID — RO. See the Intel 6 Series Chipset Specification Update for the value of the RID Register. Datasheet...
Page 621 SATA Controller Registers (D31:F5) 15.1.6 PI—Programming Interface Register (SATA–D31:F5) Address Offset: 09h Attribute: Default Value: Size: 8 bits When SCC = 01h Description This read-only bit is a 1 to indicate that the PCH supports bus master operation Reserved. Secondary Mode Native Capable (SNC) — RO. Indicates whether or not the secondary channel has a fixed mode of operation.
Page 622 SATA Controller Registers (D31:F5) 15.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F5) Address Offset: 0Dh Attribute: Default Value: Size: 8 bits Description Master Latency Timer Count (MLTC) — RO. 00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer.
Page 623 SATA Controller Registers (D31:F5) 15.1.12 SCMD_BAR—Secondary Command Block Base Address Register (SATA D31:F5) Address Offset: 18h Attribute: R/W, RO – Default Value: 00000001h Size: 32 bits Description 31:16 Reserved Base Address — R/W. This field provides the base address of the I/O space (8 15:3 consecutive I/O locations).
Page 624 SATA Controller Registers (D31:F5) 15.1.14 BAR — Legacy Bus Master Base Address Register (SATA–D31:F5) Address Offset: 20h Attribute: R/W, RO – Default Value: 00000001h Size: 32 bits The Bus Master IDE interface function uses Base Address register 5 to request a 16- byte I/O space to provide a software interface to the Bus Master functions.
Page 625 SATA Controller Registers (D31:F5) 15.1.16 SVID—Subsystem Vendor Identification Register (SATA–D31:F5) Address Offset: 2Ch Attribute: R/WO – Default Value: 0000h Size: 16 bits Lockable: Power Well: Core Function Level Reset: No Description Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware 15:0 action taken on this value.
Page 626 SATA Controller Registers (D31:F5) 15.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F5) Address Offset: Primary: 40h–41h Attribute: Secondary: 42h–43h Default Value: 0000h Size: 16 bits Description IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or Secondary decode. 0 = Disable. 1 = Enables the PCH to decode the associated Command Blocks (1F0–1F7h for primary, 170–177h for secondary) and Control Block (3F6h for primary and 376h for secondary).
Page 627 SATA Controller Registers (D31:F5) 15.1.24 PMCS—PCI Power Management Control and Status Register (SATA–D31:F5) Address Offset: 74h Attribute: RO, R/W, R/WC – Default Value: 0008h Size: 16 bits Function Level Reset:No (Bits 8 and 15 only) Bits Description PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if this bit and PMEE is set, a PME# will be generated from the SATA controller.
Page 628 SATA Controller Registers (D31:F5) 15.1.25 MAP—Address Map Register (SATA–D31:F5) Address Offset: 90h Attribute: R/W, R/WO, RO Default Value: Size: bits Function Level Reset: No (Bits 9:8 only) Bits Description 15:8 Reserved. SATA Mode Select (SMS) — R/W. Software programs these bits to control the mode in which the SATA Controller should operate.
Page 629 SATA Controller Registers (D31:F5) 15.1.26 PCS—Port Control and Status Register (SATA–D31:F5) Address Offset: 92h Attribute: R/W, RO – Default Value: 0000h Size: 16 bits Function Level Reset: No By default, the SATA ports are set to the disabled state (bits [5:0] = 0). When enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices.
Page 630 SATA Controller Registers (D31:F5) 15.1.27 SATACR0— SATA Capability Register 0 (SATA–D31:F5) Address Offset: A8h–ABh Attribute: RO, R/WO Default Value: 0010B012h Size: 32 bits Function Level Reset: No (Bits 15:8 only) Note: When SCC is 01h this register is read-only 0. Description 31:24 Reserved.
Page 631 SATA Controller Registers (D31:F5) 15.1.30 FLRCLV— FLR Capability Length and Value (SATA–D31:F5) Address Offset: B2h–B3h Attribute: RO, R/WO Default Value: 2006h Size: 16 bits Function Level Reset:No (Bits 9:8 only) When FLRCSSEL = 0, this register is defined as follows: Description 15:10 Reserved.
Page 632 SATA Controller Registers (D31:F5) 15.1.32 ATC—APM Trapping Control Register (SATA–D31:F5) Address Offset: C0h Attribute: Default Value: Size: 8 bits Note: This SATA controller does not support legacy I/O access. Therefore, this register is reserved. Software shall not change the default values of the register; otherwise, the result will be undefined.
Page 633: Bus Master Ide I/O Register Address Map
SATA Controller Registers (D31:F5) 15.2 Bus Master IDE I/O Registers (D31:F5) The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR register, located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted).
Page 634 SATA Controller Registers (D31:F5) 15.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) Address Offset: Primary: BAR + 00h Attribute: Secondary: BAR + 08h Default Value: Size: 8 bits Description Reserved. Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master transfer: This bit must NOT be changed when the bus master function is active.
Page 635 SATA Controller Registers (D31:F5) 15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5) Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO Secondary: BAR + 0Ah Default Value: Size: 8 bits Description PRD Interrupt Status (PRDIS) — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit set.
Page 636 SATA Controller Registers (D31:F5) 15.3 Serial ATA Index/Data Pair Superset Registers All of these I/O registers are in the core well. They are exposed only when SCC is 01h (that is, IDE programming interface) and the controller is not in combined mode. These are Index/Data Pair registers that are used to access the SerialATA superset registers (SerialATA Status, SerialATA Control and SerialATA Error).
Page 637 SATA Controller Registers (D31:F5) 15.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5) Address Offset: Attribute: Default Value: 00000000h Size: 32 bits SDATA when SINDX.RIDX is 00h. This is a 32-bit register that conveys the current state of the interface and host. The PCH updates it continuously and asynchronously. When the PCH transmits a COMRESET to the device, this register is updated to its reset values.
Page 638 SATA Controller Registers (D31:F5) 15.3.2.2 PxSCTL — Serial ATA Control Register (D31:F5) Address Offset: Attribute: R/W, RO Default Value: 00000004h Size: 32 bits SDATA when SINDX.RIDX is 01h. This is a 32-bit read-write register by which software controls SATA capabilities. Writes to the SControl register result in an action being taken by the PCH or the interface.
Page 639 SATA Controller Registers (D31:F5) 15.3.2.3 PxSERR—Serial ATA Error Register (D31:F5) Address Offset: Attribute: R/WC Default Value: 00000000h Size: 32 bits SDATA when SINDx.RIDX is 02h. Bits 26:16 of this register contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bits 11:0 contain error information used by host software in determining the appropriate response to the error condition.
Page 640 SATA Controller Registers (D31:F5) Description Persistent Communication or Data Integrity Error (C) — R/WC. A communication error that was not recovered occurred that is expected to be persistent. Persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes.
Page 641: Usb Ehci Pci Register Address Map (Usb Ehci-D29:F0, D26:F0)
EHCI Controller Registers (D29:F0, D26:F0) EHCI Controller Registers (D29:F0, D26:F0) 16.1 USB EHCI Configuration Registers (USB EHCI—D29:F0, D26:F0) Note: Prior to BIOS initialization of the PCH USB subsystem, the EHCI controllers will appear as Function 7. After BIOS initialization, the EHCI controllers will be Function 0. Note: Register address locations that are not shown in Table 16-1...
Page 642 Offset Address: 00h Attribute: – Default Value: 8086h Size: 16 bits Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. 16.1.2 DID—Device Identification Register (USB EHCI—D29:F0, D26:F0) Offset Address: 02h Attribute: – Default Value: See bit description...
Page 643 EHCI Controller Registers (D29:F0, D26:F0) 16.1.3 PCICMD—PCI Command Register (USB EHCI—D29:F0, D26:F0) Address Offset: 04h Attribute: R/W, RO – Default Value: 0000h Size: 16 bits Description 15:11 Reserved Interrupt Disable — R/W. 0 = The function is capable of generating interrupts. 1 = The function can not generate its interrupt to the interrupt controller.
Page 644 EHCI Controller Registers (D29:F0, D26:F0) 16.1.4 PCISTS—PCI Status Register (USB EHCI—D29:F0, D26:F0) Address Offset: 06h Attribute: R/WC, RO – Default Value: 0290h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect.
Page 645 Attribute: Default Value: See bit description Size: 8 bits Description ® Revision ID — RO. See the Intel 6 Series Chipset Specification Update for the value of the RID Register. 16.1.6 PI—Programming Interface Register (USB EHCI—D29:F0, D26:F0) Address Offset: 09h...
Page 646 EHCI Controller Registers (D29:F0, D26:F0) 16.1.9 PMLT—Primary Master Latency Timer Register (USB EHCI—D29:F0, D26:F0) Address Offset: 0Dh Attribute: Default Value: Size: 8 bits Description Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI controller is internally implemented with arbitration on an interface (and not PCI), it does not need a master latency timer.
Page 647 EHCI Controller Registers (D29:F0, D26:F0) 16.1.12 SVID—USB EHCI Subsystem Vendor ID Register (USB EHCI—D29:F0, D26:F0) Address Offset: 2Ch Attribute: – Default Value: XXXXh Size: 16 bits Reset: None Description Subsystem Vendor ID (SVID) — R/W. This register, in combination with the USB 2.0 Subsystem ID register, enables the operating system to distinguish each subsystem from the others.
Page 648 EHCI Controller Registers (D29:F0, D26:F0) 16.1.16 INT_PN—Interrupt Pin Register (USB EHCI—D29:F0, D26:F0) Address Offset: 3Dh Attribute: Default Value: See Description Size: 8 bits Description Interrupt Pin — RO. This reflects the value of D29IP.E1IP (Chipset Config Registers:Offset 3108:bits 3:0) or D26IP.E2IP (Chipset Config Registers:Offset 3114:bits 3:0).
Page 649 EHCI Controller Registers (D29:F0, D26:F0) 16.1.19 PWR_CAP—Power Management Capabilities Register (USB EHCI—D29:F0, D26:F0) Address Offset: 52h Attribute: R/W, RO – Default Value: C9C2h Size: 16 bits Description PME Support (PME_SUP) — R/W. This 5-bit field indicates the power states in which the function may assert PME#.
Page 650 EHCI Controller Registers (D29:F0, D26:F0) 16.1.20 PWR_CNTL_STS—Power Management Control/ Status Register (USB EHCI—D29:F0, D26:F0) Address Offset: 54h Attribute: R/W, R/WC, RO – Default Value: 0000h Size: 16 bits Function Level Reset: No (Bits 8 and 15 only) Description PME Status — R/WC. 0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if enabled).
Page 651 EHCI Controller Registers (D29:F0, D26:F0) 16.1.21 DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F0, D26:F0) Address Offset: 58h Attribute: Default Value: Size: 8 bits Description Debug Port Capability ID — RO. Hardwired to 0Ah indicating that this is the start of a Debug Port Capability structure.
Page 652 EHCI Controller Registers (D29:F0, D26:F0) 16.1.25 FL_ADJ—Frame Length Adjustment Register (USB EHCI—D29:F0, D26:F0) Address Offset: 61h Attribute: Default Value: Size: 8 bits Function Level Reset: No This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter.
Page 653 EHCI Controller Registers (D29:F0, D26:F0) 16.1.26 PWAKE_CAP—Port Wake Capability Register (USB EHCI—D29:F0, D26:F0) Address Offset: 62 Attribute: – Default Value: 01FFh Size: 16 bits Default Value: 07FFh Function Level Reset: No This register is in the suspend power well. The intended use of this register is to establish a policy about which ports are to be used for wake events.
Page 654 EHCI Controller Registers (D29:F0, D26:F0) 16.1.27 LEG_EXT_CAP—USB EHCI Legacy Support Extended Capability Register (USB EHCI—D29:F0, D26:F0) Address Offset: Attribute: R/W, RO – Default Value: 00000001h Size: 32 bits Power Well: Suspend Function Level Reset: No Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset. Description 31:25 Reserved —...
Page 655 EHCI Controller Registers (D29:F0, D26:F0) 16.1.28 LEG_EXT_CS—USB EHCI Legacy Support Extended Control / Status Register (USB EHCI—D29:F0, D26:F0) Address Offset: Attribute: R/W, R/WC, RO – Default Value: 00000000h Size: 32 bits Power Well: Suspend Function Level Reset: No Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset. Description SMI on BAR —...
Page 656 EHCI Controller Registers (D29:F0, D26:F0) Description SMI on BAR Enable — R/W. 0 = Disable. 1 = Enable. When this bit is 1 and SMI on BAR (D29:F0, D26:F0:6Ch, bit 31) is 1, then the host controller will issue an SMI. SMI on PCI Command Enable —...
Page 657 EHCI Controller Registers (D29:F0, D26:F0) 16.1.29 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F0, D26:F0) Address Offset: Attribute: R/W, R/WC – Default Value: 00000000h Size: 32 bits Power Well: Suspend Function Level Reset: No Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Page 658 EHCI Controller Registers (D29:F0, D26:F0) Description SMI on Periodic Enable — R/W. 0 = Disable. 1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller will issue an SMI. SMI on CF Enable — R/W. 0 = Disable.
Page 659 EHCI Controller Registers (D29:F0, D26:F0) 16.1.32 FLR_CID—Function Level Reset Capability ID (USB EHCI—D29:F0, D26:F0) Address Offset: Attribute: Default Value: Size: 8 bits Function Level Reset: No Description Capability ID — RO. 13h = If FLRCSSEL = 0 09h (Vendor Specific Capability) = If FLRCSSEL = 1 16.1.33 FLR_NEXT—Function Level Reset Next Capability Pointer (USB EHCI—D29:F0, D26:F0)
Page 660 EHCI Controller Registers (D29:F0, D26:F0) 16.1.35 FLR_CTRL—Function Level Reset Control Register (USB EHCI—D29:F0, D26:F0) Address Offset: Attribute: Default Value: Size: 8 bits Function Level Reset: No Description Reserved Initiate FLR — R/W. This bit is used to initiate FLR transition. A write of 1 initiates FLR transition.
Page 661: Enhanced Host Controller Capability Registers
EHCI Controller Registers (D29:F0, D26:F0) 16.2 Memory-Mapped I/O Registers The EHCI memory-mapped I/O space is composed of two sets of registers—Capability Registers and Operational Registers. Note: The PCH EHCI controller will not accept memory transactions (neither reads nor writes) as a target that are locked transactions. The locked transactions should not be forwarded to PCI as the address space is known to be allocated to USB.
Page 662 EHCI Controller Registers (D29:F0, D26:F0) 16.2.1.1 CAPLENGTH—Capability Registers Length Register Offset: MEM_BASE + 00h Attribute: Default Value: Size: 8 bits Description Capability Register Length Value — RO. This register is used as an offset to add to the Memory Base Register (D29:F0, D26:F0:10h) to find the beginning of the Operational Register Space.
Page 663 EHCI Controller Registers (D29:F0, D26:F0) 16.2.1.4 HCCPARAMS—Host Controller Capability Parameters Register Offset: MEM_BASE + 08h Attribute: – Default Value: 00006881h Size: 32 bits Description 31:18 Reserved Asynchronous Schedule Update Capability (ASUC) — R/W. There is no functionality associated with this bit. Periodic Schedule Update Capability (PSUC) —...
Page 664: Enhanced Host Controller Operational Register Address Map
EHCI Controller Registers (D29:F0, D26:F0) 16.2.2 Host Controller Operational Registers This section defines the enhanced host controller operational registers. These registers are located after the capabilities registers. The operational register base must be DWord-aligned and is calculated by adding the value in the first capabilities register (CAPLENGTH) to the base address of the enhanced host controller register address space (MEM_BASE).
Page 665 EHCI Controller Registers (D29:F0, D26:F0) The second set at offsets MEM_BASE + 60h to the end of the implemented register space are implemented in the Suspend power well. Unless otherwise noted, the suspend well registers are reset by the assertion of either of the following: •...
Page 666 EHCI Controller Registers (D29:F0, D26:F0) Description Interrupt on Async Advance Doorbell — R/W. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. 0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async Advance status bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register to a 1.
Page 667 EHCI Controller Registers (D29:F0, D26:F0) Description Run/Stop (RS) — R/W. 0 = Stop (default) 1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule. The Host controller continues execution as long as this bit is set. When this bit is set to 0, the Host controller completes the current transaction on the USB and then halts.
Page 668 EHCI Controller Registers (D29:F0, D26:F0) 16.2.2.2 USB2.0_STS—USB 2.0 Status Register Offset: MEM_BASE + 24h–27h Attribute: R/WC, RO Default Value: 00001000h Size: 32 bits This register indicates pending interrupts and various states of the Host controller. The status resulting from a transaction on the serial bus is not indicated in this register. See the Interrupts description in section 4 of the EHCI specification for additional information concerning USB 2.0 interrupt conditions.
Page 669 EHCI Controller Registers (D29:F0, D26:F0) Description Host System Error — R/WC. 0 = No serious error occurred during a host system access involving the Host controller module 1 = The Host controller sets this bit to 1 when a serious error occurs during a host system access involving the Host controller module.
Page 670 EHCI Controller Registers (D29:F0, D26:F0) 16.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register Offset: MEM_BASE + 28h–2Bh Attribute: Default Value: 00000000h Size: 32 bits This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host.
Page 671 EHCI Controller Registers (D29:F0, D26:F0) 16.2.2.4 FRINDEX—Frame Index Register Offset: MEM_BASE + 2Ch–2Fh Attribute: Default Value: 00000000h Size: 32 bits The SOF frame number value for the bus SOF token is derived or alternatively managed from this register. Refer to Section 4 of the EHCI specification for a detailed explanation of the SOF value management requirements on the host controller.
Page 672 EHCI Controller Registers (D29:F0, D26:F0) 16.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment Register Offset: MEM_BASE + 30h–33h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. Since the PCH hardwires the 64-bit Addressing Capability field in HCCPARAMS to 1, this register is used with the link pointers to construct 64-bit addresses to EHCI control data structures.
Page 673 EHCI Controller Registers (D29:F0, D26:F0) 16.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address Register Offset: MEM_BASE + 38h–3Bh Attribute: Default Value: 00000000h Size: 32 bits This 32-bit register contains the address of the next asynchronous queue head to be executed. Since the PCH host controller operates in 64-bit mode (as indicated by a 1 in 64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register (offset 08h).
Page 674 EHCI Controller Registers (D29:F0, D26:F0) 16.2.2.9 PORTSC—Port N Status and Control Register Offset: Port 0 RMH: MEM_BASE + 64h – Port 1 Debug Port: MEM_BASE + 68 – Port 2 USB redirect (if enabled): MEM_BASE + 6C – Attribute: R/W, R/WC, RO Default Value: 00003000h Size:...
Page 675 EHCI Controller Registers (D29:F0, D26:F0) Description Port Test Control — R/W. When this field is 0s, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value.
Page 676 EHCI Controller Registers (D29:F0, D26:F0) Description Port Reset — R/W. When software writes a 1 to this bit (from a 0), the bus reset sequence as defined in the USB Specification, Revision 2.0 is started. Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep this bit at a 1 long enough to ensure the reset sequence completes as specified in the USB Specification, Revision 2.0.
Page 677 EHCI Controller Registers (D29:F0, D26:F0) Description Force Port Resume — R/W. 0 = No resume (K-state) detected/driven on port. (Default) 1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume signaling. The Host controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state.
Page 678: Debug Port Register Address Map
EHCI Controller Registers (D29:F0, D26:F0) 16.2.3 USB 2.0-Based Debug Port Registers The Debug port’s registers are located in the same memory area, defined by the Base Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register at Configuration offset 5Ah (D29:F0, D26:F0:offset 5Ah).
Page 679 EHCI Controller Registers (D29:F0, D26:F0) 16.2.3.1 CNTL_STS—Control/Status Register Offset: MEM_BASE + A0h Attribute: R/W, R/WC, RO Default Value: 00000000h Size: 32 bits Description Reserved OWNER_CNT — R/W. 0 = Ownership of the debug port is NOT forced to the EHCI controller (Default) 1 = Ownership of the debug port is forced to the EHCI controller (that is, immediately taken away from the companion Classic USB Host controller) If the port was already owned by the EHCI controller, then setting this bit has no effect.
Page 680 EHCI Controller Registers (D29:F0, D26:F0) Description GO_CNT — R/W. 0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default) 1 = Causes hardware to perform a read or write request. NOTE: Writing a 1 to this bit when it is already set may result in undefined behavior. WRITE_READ#_CNT —...
Page 681 EHCI Controller Registers (D29:F0, D26:F0) 16.2.3.2 USBPID—USB PIDs Register Offset: MEM_BASE + A4h–A7h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits This Dword register is used to communicate PID information between the USB debug driver and the USB debug port. The debug port uses some of these fields to generate USB packets, and uses other fields to return PID information to the USB debug driver.
Page 682 EHCI Controller Registers (D29:F0, D26:F0) Datasheet...
Page 683: High Definition Audio Pci Register Address Map
Intel High Definition Audio memory- mapped space, the results are undefined. ® Note: Users interested in providing feedback on the Intel High Definition Audio specification ® or planning to implement the Intel High Definition Audio specification into a future ®...
Page 684 ® Integrated Intel High Definition Audio Controller Registers ® Table 17-1. Intel High Definition Audio PCI Register Address Map ® (Intel High Definition Audio D27:F0) (Sheet 2 of 3) Offset Mnemonic Register Name Default Type ® Intel High Definition Audio Lower Base 10h–13h...
Page 685 00h–01h Attribute: Default Value: 8086h Size: 16 bits Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 17.1.1.2 DID—Device Identification Register ® (Intel High Definition Audio Controller—D27:F0) Offset Address: 02h Attribute: –...
Page 686 NOTE: This bit does not affect the generation of MSIs. Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0. ® SERR# Enable (SERR_EN) — R/W. SERR# is not generated by the PCH Intel High Definition Audio Controller.
Page 687 1 = The Intel High Definition Audio controller sets this bit when, as a bus master, it ® receives a master abort. When set, the Intel High Definition Audio controller clears the run bit for the channel that received the abort.
Page 688 ® Integrated Intel High Definition Audio Controller Registers 17.1.1.7 SCC—Sub Class Code Register ® (Intel High Definition Audio Controller—D27:F0) Address Offset: 0Ah Attribute: Default Value: Size: 8 bits Description Sub Class Code (SCC) — RO. 03h = Audio Device 17.1.1.8 BCC—Base Class Code Register...
Page 689 High Definition Audio Controller—D27:F0) Address Offset: 14h–17h Attribute: Default Value: 00000000h Size: 32 bits Description ® Upper Base Address (UBA) — R/W. Upper 32 bits of the Base address for the Intel 31:0 High Definition Audio controller’s memory mapped configuration registers. Datasheet...
Page 690 ® Integrated Intel High Definition Audio Controller Registers 17.1.1.14 SVID—Subsystem Vendor Identification Register ® (Intel High Definition Audio Controller—D27:F0) Address Offset: 2Ch–2Dh Attribute: R/WO Default Value: 0000h Size: 16 bits Function Level Reset: No The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh), enable the operating environment to distinguish one audio subsystem from the other(s).
Page 691 ® Integrated Intel High Definition Audio Controller Registers 17.1.1.17 INTLN—Interrupt Line Register ® (Intel High Definition Audio Controller—D27:F0) Address Offset: 3Ch Attribute: Default Value: Size: 8 bits Description Interrupt Line (INT_LN) — R/W. This data is not used by the PCH. It is used to communicate to software the interrupt line that the interrupt pin is connected to.
Page 692 ® Integrated Intel High Definition Audio Controller Registers 17.1.1.20 TCSEL—Traffic Class Select Register ® (Intel High Definition Audio Controller—D27:F0) Address Offset: 44h Attribute: Default Value: Size: 8 bits Function Level Reset: No This register assigned the value to be placed in the TC field. CORB and RIRB data will always be assigned TC0.
Page 693 Reserved. ® Dock Mated (DM) — RO: This bit effectively communicates to software that an Intel HD Audio docked codec is physically and electrically attached. Controller hardware sets this bit to 1 after the docking sequence triggered by writing a 1 to the Dock Attach (GCTL.DA) bit is completed (HDA_DOCK_RST# deassertion).
Page 694 PME Enable (PMEE) — R/W. 0 = Disable ® 1 = When set and if corresponding PMES also set, the Intel High Definition Audio controller sets the PME_B0_STS bit in the GPE0_STS register (PMBASE +28h). This bit is in the resume well and is cleared on a power-on reset. Software must not make assumptions about the reset state of this bit and must set it appropriately.
Page 695 High Definition Audio Controller Registers Description Power State (PS) — R/W. This field is used both to determine the current power state ® of the Intel High Definition Audio controller and to set a new power state. 00 = D0 state 11 = D3...
Page 696 ® Integrated Intel High Definition Audio Controller Registers 17.1.1.28 MMLA—MSI Message Lower Address Register ® (Intel High Definition Audio Controller—D27:F0) Address Offset: 64h–67h Attribute: RO, R/W Default Value: 00000000h Size: 32 bits Description 31:2 Message Lower Address (MLA) — R/W. Lower address used for MSI message.
Page 697 ® Integrated Intel High Definition Audio Controller Registers 17.1.1.32 PXC—PCI Express* Capabilities Register ® (Intel High Definition Audio Controller—D27:F0) Address Offset: 72h–73h Attribute: Default Value: 0091h Size: 16 bits Description 15:14 Reserved 13:9 Interrupt Message Number (IMN) — RO. Hardwired to 0.
Page 698 D0 transition; however, it is reset by PLTRST#. This bit is not reset by Function Level Reset. ® Auxiliary Power Enable — RO. Hardwired to 0, indicating that Intel High Definition Audio device does not draw AUX power Phantom Function Enable — RO. Hardwired to 0 disabling phantom functions.
Page 699 Transactions Pending — RO. 0 = Indicates that completions for all non-posted requests have been received ® 1 = Indicates that Intel High Definition Audio controller has issued non-posted requests which have not been completed. AUX Power Detected — RO. Hardwired to 1 indicating the device is connected to resume power Unsupported Request Detected —...
Page 700 VC group. Reserved. Extended VC Count — RO. Hardwired to 001b. Indicates that 1 extended VC (in ® addition to VC0) is supported by the Intel High Definition Audio controller. 17.1.1.38 PVCCAP2 — Port VC Capability Register 2 ®...
Page 701 ® Integrated Intel High Definition Audio Controller Registers 17.1.1.40 PVCSTS—Port VC Status Register ® (Intel High Definition Audio Controller—D27:F0) Address Offset: 10Eh–10Fh Attribute: Default Value: 0000h Size: 16 bits Description 15:1 Reserved. VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not present.
Page 702 ® Integrated Intel High Definition Audio Controller Registers 17.1.1.42 VC0CTL—VC0 Resource Control Register ® (Intel High Definition Audio Controller—D27:F0) Address Offset: 114h–117h Attribute: R/W, RO Default Value: 800000FFh Size: 32 bits Function Level Reset: No Description VC0 Enable — RO. Hardwired to 1 for VC0.
Page 703 ® Integrated Intel High Definition Audio Controller Registers 17.1.1.44 VCiCAP—VCi Resource Capability Register ® (Intel High Definition Audio Controller—D27:F0) Address Offset: 11Ch–11Fh Attribute: Default Value: 00000000h Size: 32 bits Description Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for 31:24 endpoint devices.
Page 704 Size: 32 bits Description ® Port Number — RO. Hardwired to 0Fh indicating that the Intel High Definition Audio 31:24 controller is assigned as Port #15d. Component ID — RO. This field returns the value of the ESD.CID field of the chip 23:16 configuration section.
Page 705 00000001h Size: 32 bits Description ® Target Port Number — RO. The Intel High Definition Audio controller targets the 31:24 PCH’s Port 0. Target Component ID — RO. This field returns the value of the ESD.CID field of the 23:16 chip configuration section.
Page 706: High Definition Audio Memory Mapped Configuration Registers
HDBAR + Offset as indicated in Table 17-2. These memory mapped registers must be accessed in byte, word, or DWord quantities. ® Table 17-2. Intel High Definition Audio Memory Mapped Configuration Registers ® Address Map (Intel High Definition Audio D27:F0) (Sheet 1 of 4)
Page 707 ® Integrated Intel High Definition Audio Controller Registers ® Table 17-2. Intel High Definition Audio Memory Mapped Configuration Registers ® Address Map (Intel High Definition Audio D27:F0) (Sheet 2 of 4) HDBAR + Mnemonic Register Name Default Access Offset 5Ah–5Bh...
Page 708 ® Integrated Intel High Definition Audio Controller Registers ® Table 17-2. Intel High Definition Audio Memory Mapped Configuration Registers ® Address Map (Intel High Definition Audio D27:F0) (Sheet 3 of 4) HDBAR + Mnemonic Register Name Default Access Offset C4h–C7h...
Page 709 ® Integrated Intel High Definition Audio Controller Registers ® Table 17-2. Intel High Definition Audio Memory Mapped Configuration Registers ® Address Map (Intel High Definition Audio D27:F0) (Sheet 4 of 4) HDBAR + Mnemonic Register Name Default Access Offset 124h–127h...
Page 710 4401h Size: 16 bits Description Number of Output Stream Supported — R/WO. 0100b indicates that the PCH’s Intel 15:12 High Definition Audio controller supports 4 output streams. Number of Input Stream Supported — R/WO. 0100b indicates that the PCH’s Intel 11:8 High Definition Audio controller supports 4 input streams.
Page 711 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.4 OUTPAY—Output Payload Capability Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 04h Attribute: Default Value: 003Ch Size: 16 bits Description 15:7 Reserved. Output Payload Capability — RO. Hardwired to 3Ch indicating 60 word payload.
Page 712 2. When setting or clearing this bit, software must ensure that minimum link timing requirements (minimum RESET# assertion time, etc.) are met. 3. When this bit is 0 indicating that the controller is in reset, writes to all Intel High Definition Audio memory mapped registers are ignored as if the device is not present.
Page 713 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.7 WAKEEN—Wake Enable Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 0Ch Attribute: Default Value: 0000h Size: 16 bits Function Level Reset: No Description 15:4 Reserved. SDIN Wake Enable Flags — R/W. These bits control which SDI signal(s) may generate a wake event.
Page 714 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.9 GSTS—Global Status Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 10h Attribute: R/WC Default Value: 0000h Size: 16 bits Description 15:2 Reserved. Flush Status — R/WC. This bit is set to 1 by hardware to indicate that the flush cycle initiated when the Flush Control bit (HDBAR + 08h, bit 1) was set has completed.
Page 715 Global Interrupt Enable (GIE) — R/W. Global bit to enable device interrupt generation. 1 = When set to 1, the Intel High Definition Audio function is enabled to generate an interrupt. This control is in addition to any bits in the bus specific address space, such as the Interrupt Enable bit in the PCI configuration space.
Page 716 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.13 INTSTS—Interrupt Status Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 24h Attribute: Default Value: 00000000h Size: 32 bits Description Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits in this register.
Page 717 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.15 SSYNC—Stream Synchronization Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 38h Attribute: Default Value: 00000000h Size: 32 bits Description 31:8 Reserved Stream Synchronization (SSYNC) — R/W. When set to 1, these bits block data from being sent on or received from the link.
Page 718 Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware buffer within the Intel High Definition Audio controller. The hardware will physically update this bit to 1 when the CORB Pointer reset is complete. Software must read a 1 to verify that the reset completed correctly.
Page 719 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.20 CORBCTL—CORB Control Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 4Ch Attribute: Default Value: Size: 8 bits Description Reserved. Enable CORB DMA Engine — R/W. 0 = DMA stop 1 = DMA run After software writes a 0 to this bit, the hardware may not stop immediately.
Page 720 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.23 RIRBLBASE—RIRB Lower Base Address Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 50h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits Description CORB Lower Base Address — R/W. Lower address of the Response Input Ring Buffer, allowing the RIRB base address to be assigned on any 128-B boundary.
Page 721 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.26 RINTCNT—Response Interrupt Count Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 5Ah Attribute: Default Value: 0000h Size: 16 bits Description 15:8 Reserved. N Response Interrupt Count — R/W. 0000 0001b = 1 response sent to RIRB ...
Page 722 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.28 RIRBSTS—RIRB Status Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 5Dh Attribute: R/WC Default Value: Size: 8 bits Description Reserved. Response Overrun Interrupt Status — R/WC. 1 = Software sets this bit to 1 when the RIRB DMA engine is not able to write the incoming responses to memory before additional incoming responses overrun the internal FIFO.
Page 723 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.31 IR—Immediate Response Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 64h Attribute: Default Value: 00000000h Size: 32 bits Description Immediate Response Read (IRR) — RO. This register contains the response received from a codec resulting from a command sent using the Immediate Command mechanism.
Page 724 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.33 DPLBASE—DMA Position Lower Base Address Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:HDBAR + 70h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits Description DMA Position Lower Base Address — R/W. Lower 32 bits of the DMA Position Buffer Base Address.
Page 725 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.35 SDCTL—Stream Descriptor Control Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 80h Attribute: R/W, RO Input Stream[1]: HDBAR + A0h Input Stream[2]: HDBAR + C0h Input Stream[3]: HDBAR + E0h...
Page 726 ® Integrated Intel High Definition Audio Controller Registers Description Stream Run (RUN) — R/W. 0 = DMA engine associated with this input stream will be disabled. The hardware will report a 0 in this bit when the DMA engine is actually stopped. Software must read a 0 from this bit before modifying related control registers or restarting the DMA engine.
Page 727 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.36 SDSTS—Stream Descriptor Status Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 83h Attribute: R/WC, RO Input Stream[1]: HDBAR + A3h Input Stream[2]: HDBAR + C3h Input Stream[3]: HDBAR + E3h...
Page 728 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.37 SDLPIB—Stream Descriptor Link Position in Buffer ® Register (Intel High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 84h Attribute: Input Stream[1]: HDBAR + A4h Input Stream[2]: HDBAR + C4h Input Stream[3]: HDBAR + E4h...
Page 729 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.39 SDLVI—Stream Descriptor Last Valid Index Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 8Ch Attribute: Input Stream[1]: HDBAR + ACh Input Stream[2]: HDBAR + CCh Input Stream[3]: HDBAR + ECh...
Page 730 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.41 SDFIFOS—Stream Descriptor FIFO Size Register – Input Streams ® (Intel High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 90h Attribute: Input Stream[1]: HDBAR + B0h Input Stream[2]: HDBAR + D0h...
Page 731 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.43 SDFMT—Stream Descriptor Format Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 92h Attribute: Input Stream[1]: HDBAR + B2h Input Stream[2]: HDBAR + D2h Input Stream[3]: HDBAR + F2h...
Page 732 ® Integrated Intel High Definition Audio Controller Registers 17.1.2.44 SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register ® (Intel High Definition Audio Controller—D27:F0) Memory Address:Input Stream[0]: HDBAR + 98h Attribute: R/W,RO Input Stream[1]: HDBAR + B8h Input Stream[2]: HDBAR + D8h...
Page 733: Configuration Default
Integrated Digital Display Audio Registers and Verb IDs The integrated digital display ports providing audio support provide the necessary registers and interfaces for software, per the Intel High Definition Audio Specification. 17.2.1 Configuration Default Register The Configuration Default is a 32-bit register required in each Pin Widget. It is used by software as an aid in determining the configuration of jacks and devices attached to the codec.
Page 734 ® Integrated Intel High Definition Audio Controller Registers Location[5:0] indicates the physical location of the jack or device to which the pin complex is connected. This allows software to indicate, for instance, that the device is the “Front Panel Headphone Jack” as opposed to rear panel connections. The encodings...
Page 735: Port Connectivity
® Integrated Intel High Definition Audio Controller Registers Table 17-5. Port Connectivity Value Value The Port Complex is connected to a jack No physical connection for port A fixed function device (integrated speaker, integrated mic etc) is attached Both a jack and an internal device attached Table 17-6.
Page 736: Default Device
® Integrated Intel High Definition Audio Controller Registers Table 17-7. Default Device Default Device Encoding Line Out Speaker HP Out S/PDIF* Out Digital Other Side Modem Line side Modem Hand Set Side Line In Mic In Telephony S/PDIF In Digital Other In...
Page 737: Misc
Config Default register needs to be programmed in BIOS to enable or disable the audio on the port. More details of the register and other audio registers’ programming can be found in High Definition Audio Specification 1.0a at www.intel.com/standards. § §...
Page 738 ® Integrated Intel High Definition Audio Controller Registers Datasheet...
Page 739: Smbus Controller Pci Register Address Map (Smbus-D31:F3)
NOTE: Registers that are not shown should be treated as Reserved (See Section 9.2 for details). 18.1.1 VID—Vendor Identification Register (SMBus—D31:F3) Address: Attribute: – Default Value: 8086h Size: 16 bits Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel Datasheet...
Page 740 16 bits Description Device ID — RO. This is a 16-bit value assigned to the PCH SMBus controller. See the 15:0 ® Intel 6 Series Chipset Specification Update for the value of the DID Register. 18.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) Address:...
Page 741 Reserved 18.1.5 RID—Revision Identification Register (SMBus—D31:F3) Offset Address: 08h Attribute: Default Value: See bit description Size: 8 bits Description ® Revision ID — RO. See the Intel 6 Series Chipset Specification Update for the value of the RID Register. Datasheet...
Page 742 SMBus Controller Registers (D31:F3) 18.1.6 PI—Programming Interface Register (SMBus—D31:F3) Offset Address: 09h Attribute: Default Value: Size: 8 bits Description Reserved 18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3) Address Offset: 0Ah Attributes: Default Value: Size: 8 bits Description Sub Class Code (SCC) — RO. 05h = SMBus serial controller 18.1.8 BCC—Base Class Code Register (SMBus—D31:F3)
Page 743 SMBus Controller Registers (D31:F3) 18.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1 (SMBus—D31:F3) Address Offset: 14h–17h Attributes: Default Value: 00000000h Size: 32 bits Description Base Address — R/W. Provides bits 63:32 system memory base address for the PCH 31:0 SMB logic. 18.1.11 SMB_BASE—SMBus Base Address Register (SMBus—D31:F3) Address Offset: 20...
Page 744 SMBus Controller Registers (D31:F3) 18.1.13 SID—Subsystem Identification Register (SMBus—D31:F2/F4) Address Offset: 2Eh Attribute: R/WO – Default Value: 0000h Size: 16 bits Lockable: Power Well: Core Description Subsystem ID (SID) — R/WO. The SID register, in combination with the SVID register, enables the operating system (OS) to distinguish subsystems from each other.
Page 745 SMBus Controller Registers (D31:F3) 18.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3) Address Offset: 40h Attribute: Default Value: Size: 8 bits Description Reserved SSRESET – Soft SMBus Reset— R/W. 0 = The HW will reset this bit to 0 when SMBus reset operation is completed. 1 = The SMBus state machine and logic in the PCH is reset.
Page 746: Smbus I/O And Memory Mapped I/O Register Address Map
SMBus Controller Registers (D31:F3) 18.2 SMBus I/O and Memory Mapped I/O Registers The SMBus registers (see Table 18-2) can be accessed through I/O BAR or Memory BAR registers in PCI configuration space. The offsets are the same for both I/O and Memory Mapped I/O registers.
Page 747 SMBus Controller Registers (D31:F3) 18.2.1 HST_STS—Host Status Register (SMBus—D31:F3) Register Offset: SMB_BASE + 00h Attribute: R/WC, RO Default Value: Size: 8-bits All status bits are set by hardware and cleared by the software writing a one to the particular bit position. Writing a 0 to any bit position has no effect. Description Byte Done Status (DS) —...
Page 748 SMBus Controller Registers (D31:F3) Description INTR — R/WC. This bit can only be set by termination of a command. INTR is not dependent on the INTREN bit (offset SMB_BASE + 02h, bit 0) of the Host controller register (offset 02h). It is only dependent on the termination of the command. If the INTREN bit is not set, then the INTR bit will be set, although the interrupt will not be generated.
Page 749 SMBus Controller Registers (D31:F3) Description SMB_CMD — R/W. The bit encoding below indicates which command the PCH is to perform. If enabled, the PCH will generate an interrupt or SMI# when the command has completed If the value is for a non-supported or reserved command, the PCH will set the device error (DEV_ERR) status bit (offset SMB_BASE + 00h, bit 2) and generate an interrupt when the START bit is set.
Page 750 SMBus Controller Registers (D31:F3) 18.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) Register Offset: SMB_BASE + 03h Attribute: Default Value: Size: 8 bits Description This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol during the execution of any command. 18.2.4 XMIT_SLVA—Transmit Slave Address Register (SMBus—D31:F3)
Page 751 SMBus Controller Registers (D31:F3) 18.2.7 Host_BLOCK_DB—Host Block Data Byte Register (SMBus—D31:F3) Register Offset: SMB_BASE + 07h Attribute: Default Value: Size: 8 bits Description Block Data (BDTA) — R/W. This is either a register, or a pointer into a 32-byte block array, depending upon whether the E32B bit is set in the Auxiliary Control register.
Page 752 SMBus Controller Registers (D31:F3) 18.2.9 RCV_SLVA—Receive Slave Address Register (SMBus—D31:F3) Register Offset: SMB_BASE + 09h Attribute: Default Value: Size: 8 bits Lockable: Power Well: Resume Description Reserved SLAVE_ADDR — R/W. This field is the slave address that the PCH decodes for read and write cycles.
Page 753 SMBus Controller Registers (D31:F3) 18.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) Register Offset: SMB_BASE + 0Dh Attribute: Default Value: Size: 8 bits Lockable: Power Well: Resume Description Reserved Enable 32-Byte Buffer (E32B) — R/W. 0 = Disable. 1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as opposed to a single register.
Page 754 SMBus Controller Registers (D31:F3) 18.2.14 SMBus_PIN_CTL—SMBus Pin Control Register (SMBus—D31:F3) Register Offset: SMB_BASE + 0Fh Attribute: R/W, RO Default Value: See below Size: 8 bits Note: This register is in the resume well and is reset by RSMRST#. Description Reserved SMBCLK_CTL —...
Page 755 SMBus Controller Registers (D31:F3) 18.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3) Register Offset: SMB_BASE + 11h Attribute: Default Value: Size: 8 bits Note: This register is in the resume well and is reset by RSMRST#. Description Reserved SMBALERT_DIS — R/W. 0 = Allows the generation of the interrupt or SMI#. 1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT# source.
Page 756 SMBus Controller Registers (D31:F3) 18.2.18 NOTIFY_DLOW—Notify Data Low Byte Register (SMBus—D31:F3) Register Offset: SMB_BASE + 16h Attribute: Default Value: Size: 8 bits Note: This register is in the resume well and is reset by RSMRST#. Description DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received during the Host Notify protocol of the SMBus 2.0 specification.
Page 757: Pci Express* Configuration Registers Address Map
PCI Express* Configuration Registers PCI Express* Configuration Registers 19.1 PCI Express* Configuration Registers (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Note: This section assumes the default PCI Express Function Number-to-Root Port mapping is used. Function numbers for a given root port are assignable through the Root Port Function Number and Hide for PCI Express Root Ports registers (RCBA+0404h).
Page 758 PCI Express* Configuration Registers Table 19-1. PCI Express* Configuration Registers Address Map (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) (Sheet 2 of 3) Function 0–5 Offset Mnemonic Register Name Type Default 40h–41h CLIST Capabilities List 8010 42h–43h XCAP PCI Express* Capabilities 0041 R/WO, RO 44h–47h DCAP Device Capabilities 00000FE0h...
Page 759 – Default Value: 8086h Size: 16 bits Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 19.1.2 DID—Device Identification Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 02h–03h Attribute: Default Value: Port 1= Bit Description...
Page 760 PCI Express* Configuration Registers 19.1.3 PCICMD—PCI Command Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 04h–05h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Description 15:11 Reserved Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled Hot- Plug and power management events. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or power management and MSI is not enabled.
Page 761 PCI Express* Configuration Registers 19.1.4 PCISTS—PCI Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 06h Attribute: R/WC, RO – Default Value: 0010h Size: 16 bits Description Detected Parity Error (DPE) — R/WC. 0 = No parity error detected. 1 = Set when the root port receives a command or data from the backbone with a parity error.
Page 762 Attribute: Default Value: See bit description Size: 8 bits Description ® Revision ID — RO. See the Intel 6 Series Chipset Specification Update for the value of the RID Register. 19.1.6 PI—Programming Interface Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 09h Attribute:...
Page 763 PCI Express* Configuration Registers 19.1.9 CLS—Cache Line Size Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 0Ch Attribute: Default Value: Size: 8 bits Description Cache Line Size (CLS) — R/W. This is read/write but contains no functionality, per the PCI Express* Base Specification. 19.1.10 PLT—Primary Latency Timer Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Page 764 PCI Express* Configuration Registers 19.1.12 BNUM—Bus Number Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 18–1Ah Attribute: Default Value: 000000h Size: 24 bits Description Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number 23:16 below the bridge. 15:8 Secondary Bus Number (SCBN) — R/W. Indicates the bus number the port. Primary Bus Number (PBN) —...
Page 765 PCI Express* Configuration Registers 19.1.15 SSTS—Secondary Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 1Eh–1Fh Attribute: R/WC Default Value: 0000h Size: 16 bits Description Detected Parity Error (DPE) — R/WC. 0 = No error. 1 = The port received a poisoned TLP. Received System Error (RSE) —...
Page 766 PCI Express* Configuration Registers 19.1.16 MBL—Memory Base and Limit Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 20h–23h Attribute: Default Value: 00000000h Size: 32 bits Accesses that are within the ranges specified in this register will be sent to the attached device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7:04:bit 1) is set. Accesses from the attached device that are outside the ranges specified will be forwarded to the backbone if CMD.BME (D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7:04:bit 2) is set.
Page 767 PCI Express* Configuration Registers 19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/ F7/F6/F7) Address Offset: 28h–2Bh Attribute: Default Value: 00000000h Size: 32 bits Description Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the 31:0 prefetchable address base. 19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/...
Page 768 PCI Express* Configuration Registers 19.1.21 INTR—Interrupt Information Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 3Ch–3Dh Attribute: R/W, RO Default Value: See bit description Size: 16 bits Function Level Reset: No (Bits 7:0 only) Description Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the root port. At reset, this register takes on the following values that reflect the reset state of the D28IP register in chipset config space: Port...
Page 769 PCI Express* Configuration Registers 19.1.22 BCTRL—Bridge Control Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 3Eh–3Fh Attribute: Default Value: 0000h Size: 16 bits Description 15:12 Reserved Discard Timer SERR# Enable (DTSE): Reserved per PCI Express* Base Specification, Revision 1.0a Discard Timer Status (DTS): Reserved per PCI Express* Base Specification, Revision 1.0a.
Page 770 PCI Express* Configuration Registers 19.1.23 CLIST—Capabilities List Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 40–41h Attribute: Default Value: 8010h Size: 16 bits Description 15:8 Next Capability (NEXT) — RO. Value of 80h indicates the location of the next pointer. Capability ID (CID) — RO. Indicates this is a PCI Express* capability. 19.1.24 XCAP—PCI Express* Capabilities Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Page 771 PCI Express* Configuration Registers 19.1.25 DCAP—Device Capabilities Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 44h–47h Attribute: Default Value: 00008000h Size: 32 bits Description 31:28 Reserved 27:26 Captured Slot Power Limit Scale (CSPS) — RO. Not supported. 25:18 Captured Slot Power Limit Value (CSPV) — RO. Not supported. 17:16 Reserved Role Based Error Reporting (RBER) —...
Page 772 PCI Express* Configuration Registers 19.1.26 DCTL—Device Control Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 48h–49h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Description Reserved 14:12 Max Read Request Size (MRRS) — RO. Hardwired to 0. Enable No Snoop (ENS) — RO. Not supported. The root port will never issue non-snoop requests.
Page 773 PCI Express* Configuration Registers 19.1.27 DSTS—Device Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 4Ah–4Bh Attribute: R/WC, RO Default Value: 0010h Size: 16 bits Description 15:6 Reserved Transactions Pending (TDP) — RO. This bit has no meaning for the root port since only one transaction may be pending to the PCH, so a read of this bit cannot occur until it has already returned to 0.
Page 774 PCI Express* Configuration Registers 19.1.28 LCAP—Link Capabilities Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 4Ch Attribute: R/WO, RO – Default Value: See bit description Size: 32 bits Description Port Number (PN) — RO. Indicates the port number for the root port. This value is different for each implemented port: Function Port #...
Page 775 PCI Express* Configuration Registers Description Active State Link PM Support (APMS) — R/WO. Indicates what level of active state link power management is supported on the root port. Bits Definition Neither L0s nor L1 are supported 11:10 L0s Entry Supported L1 Entry Supported Both L0s and L1 Entry Supported Maximum Link Width (MLW) —...
Page 776 PCI Express* Configuration Registers 19.1.29 LCTL—Link Control Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 50h–51h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Description 15:10 Reserved Hardware Autonomous Width Disable – RO. Hardware never attempts to change the link width except when attempting to correct unreliable Link operation. Reserved Extended Synch (ES) —...
Page 777 PCI Express* Configuration Registers 19.1.30 LSTS—Link Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 52h–53h Attribute: Default Value: See bit description Size: 16 bits Description 15:14 Reserved Data Link Layer Active (DLLA) — RO. Default value is 0b. 0 = Data Link Control and Management State Machine is not in the DL_Active state 1 = Data Link Control and Management State Machine is in the DL_Active state Slot Clock Configuration (SCC) —...
Page 778 PCI Express* Configuration Registers 19.1.31 SLCAP—Slot Capabilities Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 54h Attribute: R/WO, RO – Default Value: 00040060h Size: 32 bits Description Physical Slot Number (PSN) — R/WO. This is a value that is unique to the slot 31:19 number.
Page 779 PCI Express* Configuration Registers 19.1.32 SLCTL—Slot Control Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 58h Attribute: R/W, RO – Default Value: 0000h Size: 16 bits Description 15:13 Reserved Link Active Changed Enable (LACE) — R/W. When set, this field enables generation of a hot plug interrupt when the Data Link Layer Link Active field (D28:F0/F1/F2/F3/F4/ F5/F6/F7:52h:bit 13) is changed.
Page 780 PCI Express* Configuration Registers 19.1.33 SLSTS—Slot Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 5Ah Attribute: R/WC, RO – Default Value: 0000h Size: 16 bits Description 15:9 Reserved Link Active State Changed (LASC) — R/WC. 1 = This bit is set when the value reported in Data Link Layer Link Active field of the Link Status register (D28:F0/F1/F2/F3/F4/F5/F6/F7:52h:bit 13) is changed.
Page 781 PCI Express* Configuration Registers 19.1.34 RCTL—Root Control Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 5Ch Attribute: – Default Value: 0000h Size: 16 bits Description 15:4 Reserved PME Interrupt Enable (PIE) — R/W. 0 = Interrupt generation disabled. 1 = Interrupt generation enabled when PCISTS.Inerrupt Status (D28:F0/F1/F2/F3/F4/ F5/F6/F7:60h, bit 16) is in a set state (either due to a 0 to 1 transition, or due to this bit being set with RSTS.IS already set).
Page 782 PCI Express* Configuration Registers 19.1.36 DCAP2—Device Capabilities 2 Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 64h Attribute: – Default Value: 00000016h Size: 32 bits Description 31:5 Reserved Completion Timeout Disable Supported (CTDS) — RO. A value of 1b indicates support for the Completion Timeout Disable mechanism. Completion Timeout Ranges Supported (CTRS) –...
Page 783 PCI Express* Configuration Registers 19.1.38 LCTL2—Link Control 2 Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 70h Attribute: – Default Value: 0001h Size: 16 bits Description 15:4 Reserved Target Link Speed (TLS)— R/W. This field sets an upper limit on Link operational speed by restricting the values advertised by the upstream component in its training sequences.
Page 784 PCI Express* Configuration Registers 19.1.41 MA—Message Signaled Interrupt Message Address Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 84h Attribute: – Default Value: 00000000h Size: 32 bits Description Address (ADDR) — R/W. Lower 32 bits of the system specified message address, 31:2 always DW aligned. Reserved 19.1.42 MD—Message Signaled Interrupt Message Data Register...
Page 785 PCI Express* Configuration Registers 19.1.45 PMCAP—Power Management Capability Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: A0h Attribute: – Default Value: 0001h Size: 16 bits Description 15:8 Next Capability (NEXT) — RO. Indicates this is the last item in the list. Capability Identifier (CID) — RO. Value of 01h indicates this is a PCI power management capability.
Page 786 PCI Express* Configuration Registers 19.1.47 PMCS—PCI Power Management Control and Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: A4h Attribute: R/W, RO – Default Value: 00000000h Size: 32 bits Description 31:24 Reserved Bus Power / Clock Control Enable (BPCE) — Reserved per PCI Express* Base Specification, Revision 1.0a.
Page 787 PCI Express* Configuration Registers 19.1.48 MPC2—Miscellaneous Port Configuration Register 2 (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: D4h Attribute: R/W, RO – Default Value: 00000000h Size: 32 bits Description 31:6 Reserved PCIe 2.0 Compliance Mode Enable (PCME) — R/W. 0 = Compliance mode is disabled. 1 = With proper termination PCH PCIe ports will transmit compliance pattern.
Page 788 PCI Express* Configuration Registers 19.1.49 MPC—Miscellaneous Port Configuration Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: D8h Attribute: R/W, RO – Default Value: 08110000h Size: 32 bits Description Power Management SCI Enable (PMCE) — R/W. 0 = SCI generation based on a power management event is disabled. 1 = Enables the root port to generate SCI whenever a power management event is detected.
Page 789 PCI Express* Configuration Registers Description Detect Override (FORCEDET) — R/W. 0 = Normal operation. Detected output from AFE is sampled for presence detection. 1 = Override mode. Ignores AFE detect output and link training proceeds as if a device were detected. Flow Control During L1 Entry (FCDL1E) —...
Page 790 PCI Express* Configuration Registers Description Bridge Type (BT) — R/WO. This register can be used to modify the Base Class and Header Type fields from the default PCI-to-PCI bridge to a Host Bridge. Having the root port appear as a Host Bridge is useful in some server configurations. 0 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 04h, and Header Type = Type 1.
Page 791 PCI Express* Configuration Registers 19.1.51 RPDCGEN—Root Port Dynamic Clock Gating Enable (PCI Express—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: E1h Attribute: Default Value: Size: 8-bits Bits Description Reserved. RO Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) — R/W. 0 = Disables dynamic clock gating of the shared resource link clock domain. 1 = Enables dynamic clock gating on the root port shared resource link clock domain.
Page 792 PCI Express* Configuration Registers 19.1.53 PECR3—PCI Express* Configuration Register 3 (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: ECh–EFh Attribute: Default Value: 00000000h Size: 32 bits Description 31:2 Reserved Subtractive Decode Compatibility Device ID (SDCDID) — R/W. 0 = This function reports the device Device ID value assigned to the PCI Express Root Ports listed in Section 1 = This function reports a Device ID of 244Eh for desktop or 2448h for mobile.
Page 793 PCI Express* Configuration Registers 19.1.54 UES—Uncorrectable Error Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 104h 107h Attribute: R/WC, RO – Default Value: 00000000000x0xxx0x0x0000000x0000b Size: 32 bits This register maintains its state through a platform reset. It loses its state upon suspend. Description 31:21 Reserved...
Page 794 PCI Express* Configuration Registers 19.1.55 UEM—Uncorrectable Error Mask (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 108h 10Bh Attribute: R/WO, RO – Default Value: 00000000h Size: 32 bits When set, the corresponding error in the UES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Description 31:21 Reserved...
Page 795 PCI Express* Configuration Registers Description Data Link Protocol Error Mask (DLPE) — R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. Reserved Training Error Mask (TE) — RO. Training Errors not supported 19.1.56 UEV —...
Page 796 PCI Express* Configuration Registers 19.1.57 CES — Correctable Error Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 110h 113h Attribute: R/WC – Default Value: 00000000h Size: 32 bits Description 31:14 Reserved Advisory Non-Fatal Error Status (ANFES) — R/WC. 0 = Advisory Non-Fatal Error did not occur. 1 = Advisory Non-Fatal Error did occur.
Page 797 PCI Express* Configuration Registers 19.1.59 AECC — Advanced Error Capabilities and Control Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 118h 11Bh Attribute: – Default Value: 00000000h Size: 32 bits Description 31:9 Reserved ECRC Check Enable (ECE) — RO. ECRC is not supported. ECRC Check Capable (ECC) —...
Page 798 PCI Express* Configuration Registers 19.1.61 PECR2 — PCI Express* Configuration Register 2 (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 320–323h Attribute: Default Value: 60005007h Size: 32 bits Description 31:20 Reserved PECR2 Field 1 — R/W. BIOS must set this bit to 1b. 20:0 Reserved 19.1.62 PEETM —...
Page 799: Memory-Mapped Registers
High Precision Event Timer Registers High Precision Event Timer Registers The timer registers are memory-mapped in a non-indexed scheme. This allows the processor to directly access each register without having to use an index register. The timer register space is 1024 bytes. The registers are generally aligned on 64-bit boundaries to simplify implementation with IA64 processors.
Page 800 High Precision Event Timer Registers Table 20-1. Memory-Mapped Registers (Sheet 2 of 2) Offset Mnemonic Register Default Type 130–13Fh — Reserved — — 140–147h TIM2_CONF Timer 2 Configuration and Capabilities R/W, RO 148–14Fh TIM2_COMP Timer 2 Comparator Value 150–15Fh — Reserved —...
Page 801 (69.841279 ns). Vendor ID Capability (VENDOR_ID_CAP) — RO. This is a 16-bit value assigned to 31:16 Intel. Legacy Replacement Rout Capable (LEG_RT_CAP) — RO. Hardwired to 1. Legacy Replacement Interrupt Rout option is supported. Reserved. This bit returns 0 when read.
Page 802 High Precision Event Timer Registers 20.1.3 GINTR_STA—General Interrupt Status Register Address Offset: 020h Attribute: R/WC Default Value: 00000000 00000000h Size: 64 bits Description 63:8 Reserved. These bits will return 0 when read. Timer 7 Interrupt Active (T07_INT_STS) — R/WC. Same functionality as Timer 0. Timer 6 Interrupt Active (T06_INT_STS) —...
Page 803 High Precision Event Timer Registers 20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register Address Offset: Timer 0: 100–107h, Attribute: RO, R/W Timer 1: 120–127h, Timer 2: 140–147h, Timer 3: 160–167h, Timer 4: 180–187h, Timer 5: 1A0–1A7h, Timer 6: 1C0–1C7h, Timer 7: 1E0–1E7h, Default Value: Size:...
Page 804 High Precision Event Timer Registers Description Timer n Interrupt Rout (Tn_INT_ROUT_CNF) — R/W / RO. This 5-bit field indicates the routing for the interrupt to the 8259 or I/O (x) APIC. Software writes to this field to select which interrupt in the 8259 or I/O (x) will be used for this timer’s interrupt.
Page 805 High Precision Event Timer Registers Description Timer n Type (TIMERn_TYPE_CNF) — R/W or RO. Timer 0:Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 = Enable timer to generate a periodic interrupt. Timers 1, 2, 3, 4, 5, 6, 7: Hardwired to 0. Writes have no affect. Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) —...
Page 806 High Precision Event Timer Registers 20.1.6 TIMn_COMP—Timer n Comparator Value Register Address Offset: Timer 0: 108h–10Fh, Timer 1: 128h–12Fh, Timer 2: 148h–14Fh, Timer 3: 168h–16Fh, Timer 4: 188h – 18Fh, Timer 5: 1A8h – 1AFh, Timer 6: 1C8h – 1CFh, Timer 7: 1E8h –...
Page 807 High Precision Event Timer Registers 20.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message Interrupt Rout Register Address Offset: Timer 0: 110–117h, Attribute: Timer 1: 130–137h, Timer 2: 150–157h, Timer 3: 170–177h, Timer 4: 190–197h, Timer 5: 1B0–1B7h, Timer 6: 1D0–1D7h, Timer 7: 1F0–1F7h, Default Value: Size: 64 bit...
Page 808 High Precision Event Timer Registers Datasheet...
Page 809: Serial Peripheral Interface (Spi) Register Address Map
Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) The Serial Peripheral Interface resides in memory mapped space. This function contains registers that allow for the setup and programming of devices that reside on the SPI interface. Note: All registers in this function (including memory-mapped registers) must be addressable in byte, word, and DWord quantities.
Page 810 Serial Peripheral Interface (SPI) Table 21-1. Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers) (Sheet 2 of 2) SPIBAR + Mnemonic Register Name Default Offset 78h–7Bh FPR1 Flash Protected Range 1 00000000h 7Ch–7Fh FPR2 Flash Protected Range 2 00000000h 80–83h FPR3...
Page 811 Flash Descriptor Override Pin-Strap Status (FDOPSS) — RO. This bit indicates the condition of the Flash Descriptor Security Override / Intel ME Debug Mode Pin-Strap. 0 = The Flash Descriptor Security Override / Intel ME Debug Mode strap is set using external pull-up on HDA_SDO...
Page 812 This bit remains asserted until cleared by software writing a 1 or until ® hardware reset occurs due to a global reset or host partition reset in an Intel enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in this register.
Page 813 Serial Peripheral Interface (SPI) 21.1.3 HSFC—Hardware Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 06hAttribute: R/W, R/WS Default Value: 0000hSize: 16 bits Note: This register is only applicable when SPI device is in descriptor mode. Description Flash SPI SMI# Enable (FSMIE) —...
Page 814 Serial Peripheral Interface (SPI) 21.1.5 FDATA0—Flash Data 0 Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 10h Attribute: Default Value: 00000000h Size: 32 bits Description Flash Data 0 (FD0) — R/W. This field is shifted out as the SPI Data on the Master-Out Slave-In Data pin during the data portion of the SPI cycle.
Page 815 Master[7:0]. BIOS can grant one or more masters write access to the BIOS region 1 overriding the permissions in the Flash Descriptor. 31:24 ® Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is Host processor/GbE. Master[0] and Master[7:4] are reserved. The contents of this register are locked by the FLOCKDN bit.
Page 816 Serial Peripheral Interface (SPI) 21.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 54h Attribute: Default Value: 00000000h Size: 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Description 31:29 Reserved...
Page 817 Serial Peripheral Interface (SPI) ® 21.1.10 FREG2—Flash Region 2 (Intel ME) Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 5Ch Attribute: Default Value: 00000000h Size: 32 bits Note: This register is only applicable when SPI device is in descriptor mode.
Page 818 Serial Peripheral Interface (SPI) 21.1.12 FREG4—Flash Region 4 (Platform Data) Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 64h Attribute: Default Value: 00000000h Size: 32 bits Note: This register is only applicable when SPI device is in descriptor mode. Description 31:29 Reserved...
Page 819 Serial Peripheral Interface (SPI) 21.1.14 PR1—Protected Range 1 Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 78h Attribute: Default Value: 00000000h Size: 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Description Write Protection Enable —...
Page 820 Serial Peripheral Interface (SPI) 21.1.15 PR2—Protected Range 2 Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 7Ch Attribute: Default Value: 00000000h Size: 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Description Write Protection Enable —...
Page 821 Serial Peripheral Interface (SPI) 21.1.17 PR4—Protected Range 4 Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 84h Attribute: Default Value: 00000000h Size: 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Description Write Protection Enable —...
Page 822 This bit remains asserted until cleared by software writing a 1 or ® hardware reset due to a global reset or host partition reset in an Intel ME enabled system.
Page 823 Serial Peripheral Interface (SPI) 21.1.19 SSFC—Software Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 91h Attribute: Default Value: F80000h Size: 24 bits Description 23:19 Reserved – BIOS must set this field to ‘11111’b SPI Cycle Frequency (SCF) — R/W. This register sets frequency to use for all SPI software sequencing cycles (write, erase, fast read, read status, etc.) except for the read cycle which always run at 20 MHz.
Page 824 Serial Peripheral Interface (SPI) 21.1.20 PREOP—Prefix Opcode Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 94h Attribute: Default Value: 0000h Size: 16 bits Description Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is 15:8 permitted to run as the first command in an atomic cycle sequence.
Page 825 Serial Peripheral Interface (SPI) 21.1.22 OPMENU—Opcode Menu Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + 98h Attribute: Default Value: 0000000000000000h Size: 64 bits Eight entries are available in this register to give BIOS a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do.
Page 826 Serial Peripheral Interface (SPI) 21.1.23 BBAR—BIOS Base Address Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + A0h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits Eight entries are available in this register to give BIOS a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do.
Page 827 Serial Peripheral Interface (SPI) 21.1.25 FDOD—Flash Descriptor Observability Data Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + B4h Attribute: Default Value: 00000000h Size: 32 bits Note: This register that can be used to observe the contents of the Flash Descriptor that is stored in the PCH Flash Controller.
Page 828 Serial Peripheral Interface (SPI) Description Write Enable on Write Status (LWEWS) — R/W. This register is locked by the Vendor Component Lock (LVCL) bit. 0 = No automatic write of 00h will be made to the SPI flash’s status register) 1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the SPI flash.
Page 829 Serial Peripheral Interface (SPI) 21.1.28 UVSCC— Host Upper Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + C8h Attribute: RO, R/WL Default Value: 00000000h Size: 32 bits Note: All attributes described in UVSCC must apply to all flash space equal to or above the FPBA, even if it spans between two separate flash parts.
Page 830 Serial Peripheral Interface (SPI) Description Upper Write Granularity (UWG) — R/W. This register is locked by the Vendor Component Lock (UVCL) bit. 0 = 1 Byte 1 = 64 Byte NOTES: If more than one Flash component exists, this field must be set to the lowest common write granularity of the different Flash components.
Page 831 Serial Peripheral Interface (SPI) 21.1.30 SRDL — Soft Reset Data Lock (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + F0h Attribute: R/WL Default Value: 00000000h Size: 32 bits Description 31:1 Reserved. Set_Stap Lock (SSL) — R/WL. 0 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers are writeable.
Page 832: Gigabit Lan Spi Flash Program Register Address Map
Serial Peripheral Interface (SPI) 21.2 Flash Descriptor Records The following sections describe the data structure of the Flash Descriptor on the SPI device. These are not registers within the PCH. 21.3 OEM Section Memory Address: F00h Default Value: Size: 256 Bytes 256 Bytes are reserved at the top of the Flash Descriptor for use by the OEM.
Page 833 Flash Descriptor Override Pin Strap Status (FDOPSS)— RO. This bit indicates the condition of the Flash Descriptor Security Override / Intel ME Debug Mode Pin-Strap. 0 = The Flash Descriptor Security Override / Intel ME Debug Mode strap is set using external pull-up on HDA_SDO...
Page 834 This bit remains asserted until cleared by software writing a 1 or until ® hardware reset occurs due to a global reset or host partition reset in an Intel enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in this register.
Page 835 Serial Peripheral Interface (SPI) 21.4.3 HSFC—Hardware Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 06h Attribute: R/W, R/WS Default Value: 0000h Size: 16 bits Description 15:10 Reserved Flash Data Byte Count (FDBC) — R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle.
Page 836 Serial Peripheral Interface (SPI) 21.4.4 FADDR—Flash Address Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 08h Attribute: Default Value: 00000000h Size: 32 bits Description 31:25 Reserved Flash Linear Address (FLA) — R/W. The FLA is the starting byte linear address of a 24:0 SPI Read or Write cycle or an address within a Block for the Block Erase command.
Page 837 Master[3:1]. GbE can grant one or more masters write access to the GbE region 3 overriding the permissions in the Flash Descriptor. 27:25 ® Master[1] is Host Processor/BIOS, Master[2] is Intel Management Engine, Master[3] is Host processor/GbE. The contents of this register are locked by the FLOCKDN bit.
Page 838 Region Base (RB) — RO. This specifies address bits 24:12 for the Region 1 Base 12:0 The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base. ® 21.4.9 FREG2—Flash Region 2 (Intel ME) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 5Ch Attribute:...
Page 839 Serial Peripheral Interface (SPI) 21.4.10 FREG3—Flash Region 3 (GbE) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 60h Attribute: Default Value: 00000000hSize: 32 bits Description 31:29 Reserved Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 3 Limit. 28:16 The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Limit.
Page 840 Serial Peripheral Interface (SPI) 21.4.12 PR1—Protected Range 1 Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 78h Attribute: Default Value: 00000000h Size: 32 bits Note: This register can not be written when the FLOCKDN bit is set to 1. Description Write Protection Enable —...
Page 841 This bit remains asserted until cleared by software writing a 1 or ® hardware reset due to a global reset or host partition reset in an Intel ME enabled system.
Page 842 Serial Peripheral Interface (SPI) 21.4.14 SSFC—Software Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 91h Attribute: Default Value: 000000h Size: 24 bits Description 23:19 Reserved SPI Cycle Frequency (SCF) — R/W. This register sets frequency to use for all SPI software sequencing cycles (write, erase, fast read, read status, etc.) except for the read cycle which always run at 20 MHz.
Page 843 Serial Peripheral Interface (SPI) 21.4.15 PREOP—Prefix Opcode Configuration Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 94h Attribute: Default Value: 0000h Size: 16 bits Description Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is 15:8 permitted to run as the first command in an atomic cycle sequence.
Page 844 Serial Peripheral Interface (SPI) 21.4.17 OPMENU—Opcode Menu Configuration Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 98h Attribute: Default Value: 0000000000000000h Size: 64 bits Eight entries are available in this register to give GbE a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do.
Page 845: Thermal Sensor Register Address Map
Thermal Sensor Registers (D31:F6) Thermal Sensor Registers (D31:F6) 22.1 PCI Bus Configuration Registers Table 22-1. Thermal Sensor Register Address Map Offset Mnemonic Register Name Default Type 00h–01h Vendor Identification 8086h 02h–03h Device Identification 1C24h 04h–05h Command Register 0000h R/W, RO 06h–07h Device Status 0010h...
Page 846 Default Value: 8086h Size: 16 bit Lockable: Power Well: Core Description 15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 22.1.2 DID—Device Identification Offset Address: 02h Attribute: – Default Value: 1C24h Size:...
Page 847 Thermal Sensor Registers (D31:F6) 22.1.4 STS—Status Address Offset: 06h Attribute: R/WC, RO – Default Value: 0010h Size: 16 bits Description Detected Parity Error (DPE) — R/WC. This bit is set whenever a parity error is seen on the internal interface for this function, regardless of the setting of bit 6 in the command register.
Page 848 Thermal Sensor Registers (D31:F6) 22.1.7 SCC—Sub Class Code Address Offset: 0Ah Attribute: Default Value: Size: 8 bits Description Sub Class Code (SCC) — RO. Value assigned to the PCH Thermal logic. 22.1.8 BCC—Base Class Code Address Offset: 0Bh Attribute: Default Value: Size: 8 bits Description...
Page 849 Thermal Sensor Registers (D31:F6) 22.1.12 TBAR—Thermal Base Address Offset: 10h Attribute: R/W, RO – Default Value: 00000004h Size: 32 bits This BAR creates 4K bytes of memory space to signify the base address of Thermal memory mapped configuration registers. This memory space is active when the Command (CMD) register Memory Space Enable (MSE) bit is set and either TBAR[31:12] or TBARH are programmed to a non-zero address.
Page 850 Thermal Sensor Registers (D31:F6) 22.1.15 SID—Subsystem ID Address Offset: 2Eh Attribute: R/WO – Default Value: 0000h Size: 16 bits This register should be implemented for any function that could be instantiated more than once in a given system. The SID register, in combination with the Subsystem Vendor ID register make it possible for the operating environment to distinguish one subsystem from the other(s).
Page 851 Thermal Sensor Registers (D31:F6) 22.1.19 TBARB—BIOS Assigned Thermal Base Address Address Offset: 40h Attribute: R/W,RO – Default Value: 00000004h Size: 32 bits This BAR creates 4 KB of memory space to signify the base address of Thermal memory mapped configuration registers. This memory space is active when TBARB.SPTYPEN is asserted.
Page 852 Thermal Sensor Registers (D31:F6) 22.1.21 PID—PCI Power Management Capability ID Address Offset: 50h Attribute: – Default Value: 0001h Size: 16 bits Description Next Capability (NEXT) — RO. Indicates that this is the last capability structure in 15:8 the list. Cap ID (CAP) — RO. Indicates that this pointer is a PCI power management capability 22.1.22 PC—Power Management Capabilities Address Offset: 52h...
Page 853 Thermal Sensor Registers (D31:F6) 22.1.23 PCS—Power Management Control And Status Address Offset: 54h Attribute: R/W, RO – Default Value: 0008h Size: 32 bits Description 31:24 Data — RO. Does not apply. Hardwired to 0s. Bus Power/Clock Control Enable (BPCCE) — RO. Hardwired to 0. B2/B3 Support (B23) —...
Page 854: Thermal Memory Mapped Configuration Register Address Map
Thermal Sensor Registers (D31:F6) 22.2 Thermal Memory Mapped Configuration Registers (Thermal Sensor – D31:F26) The base memory for these thermal memory mapped configuration registers is specified in the TBARB (D31:F6:Offset 40h). The individual registers are then accessible at TBARB + Offset. Table 22-2.
Page 855 Thermal Sensor Registers (D31:F6) 22.2.1 TSIU—Thermal Sensor In Use Offset Address: TBARB+00h Attribute: RO, R/W Default Value: Size: 8 bit Description Reserved. Thermal Sensor In Use (TSIU) — R/W. This is a SW semaphore bit. After a core well reset, a read to this bit returns a 0. After the first read, subsequent reads will return a 1.
Page 856 Thermal Sensor Registers (D31:F6) 22.2.4 TSTR — Thermal Sensor Thermometer Read Offset Address: TBARB+03h Attribute: Default Value: Size: 8 bit This register generally provides the calibrated temperature from the thermometer circuit when the thermometer is enabled. Description Thermometer Reading (TR)— RO. Value corresponds to the thermal sensor temperature.
Page 857 Thermal Sensor Registers (D31:F6) 22.2.7 TSES—Thermal Sensor Error Status Offset Address: TBARB+0Ch Attribute: R/WC Default Value: Size: 8 bit Description Auxiliary2 High-to-LowEvent — R/WC. 0 = No trip occurs. 1 = Indicates that an Auxiliary2 Thermal Sensor trip event occurred based on a higher to lower temperature transition through the trip point.
Page 858 Thermal Sensor Registers (D31:F6) 22.2.8 TSGPEN—Thermal Sensor General Purpose Event Enable Offset Address: TBARB+0Dh Attribute: Default Value: Size: 8 bit This register controls the conditions that result in General Purpose events to be signalled from Thermal Sensor trip events. Description Auxiliary2 High-to-Low Enable —...
Page 859 Thermal Sensor Registers (D31:F6) 22.2.9 TSPC—Thermal Sensor Policy Control Offset Address: TBARB+0Eh Attribute: R/W, RO Default Value: Size: 8 bit Description Policy Lock-Down Bit — R/W. 0 = This register can be programmed and modified. 1 = Prevents writes to this register and TSTTP.bits [31:16] (offset 04h). NOTE: TSCO.bit 7 (offset 08h) and TSLOCK.bit2 (offset 83h) must also be 1 when this bit is set to 1.
Page 860 Thermal Sensor Registers (D31:F6) 22.2.10 PTA—PCH Temperature Adjust Offset Address: TBARB+14h Attribute: Default Value: 0000h Size: 16 bit Description PCH Slope — R/W. This field contains the PCH slope for calculating PCH temperature. 15:8 The bits are locked by AE.bit7 (offset 3Fh). NOTE: When thermal reporting is enabled, BIOS must write DEh into this field.
Page 861 Thermal Sensor Registers (D31:F6) 22.2.12 AE—Alert Enable Offset Address: TBARB+3Fh Attribute: Default Value: Size: 8 bit Description Lock Enable — R/W. 0 = Lock Disabled. 1 = Lock Enabled. This will lock this register (including this bit) This bit is reset by a Host Partitioned Reset. Note that CF9 warm reset is a Host Partitioned Reset.
Page 862 Default state for this register is PHL disabled (00h). For utilizing the PCHHOT# functionality, a soft strap has to be configured and BIOS programs this PHL value. Please refer to the SPI Flash Programming Guide Application Note and Intel ME FW collaterals for information on enabling PCHHOT#.
Page 863 Thermal Sensor Registers (D31:F6) Description Auxiliary2 Low-to-High Enable — R/W. 0 = Corresponding status bit does not result in PCI interrupt. 1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal Error Status Register. Catastrophic Low-to-High Enable —...
Page 864 Thermal Sensor Registers (D31:F6) 22.2.19 TTC2—Thermal Compares 2 Offset Address: TBARB+ACh Attribute: Default Value: 00000000h Size: 32 bit Bits [31:16] of this register are set when an external controller (such as EC) does the Write DIMM Temp Limits Command. Refer to Section 5.21.2 for more information.
Page 865 Thermal Sensor Registers (D31:F6) 22.2.21 ITV—Internal Temperature Values Offset Address: TBARB+D8h Attribute: Default Value: 00000000h Size: 32 bit Description 31:24 Reserved Sequence Number — RO. Provides a sequence number which can be used by the host to detect if the ME FW has hung. The value will roll over to 00h from FFh. The count is updated at approximately 200 ms.
Page 866 Thermal Sensor Registers (D31:F6) Datasheet...
Page 867: Intel (Mei - D22:F0)
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) ® Intel Management Engine Interface (MEI) Subsystem Registers (D22:F0) ® 23.1 First Intel Management Engine Interface (Intel MEI) Configuration Registers (MEI — D22:F0) ® Table 23-1. Intel MEI Configuration Registers Address Map (MEI —...
Page 868 Default Value: See bit description Size: 16 bits Description Device ID (DID) — RO. This is a 16-bit value assigned to the Intel Management ® 15:0 Engine Interface controller. See the Intel 6 Series Chipset Specification Update for the value of the DID Register.
Page 869 H_PCI_CSR register to generate an ME MSI. When this bit is 0, Intel MEI is blocked from generating MSI to the host processor. NOTE: This bit does not block Intel MEI accesses to ME-UMA; that is, writes or reads to the host and ME circular buffers through the read window and write window registers still cause ME backbone transactions to ME-UMA.
Page 870 24 bits Description 23:16 Base Class Code (BCC) — RO. Indicates the base class code of the Intel MEI device. 15:8 Sub Class Code (SCC) — RO. Indicates the sub class code of the Intel MEI device. Programming Interface (PI) — RO. Indicates the programming interface of the Intel MEI device.
Page 871 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.1.8 MEI0_MBAR—MEI0 MMIO Base Address Register (MEI—D22:F0) Address Offset: 10h Attribute: R/W, RO – Default Value: 0000000000000004h Size: 64 bits This register allocates space for the MEI0 memory mapped registers. Description Base Address (BA) — R/W. Software programs this field with the base address of 63:4 this region.
Page 872 0400h Size: 16 bits Description Interrupt Pin (IPIN) — RO. This indicates the interrupt pin the Intel MEI host 15:8 controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively. Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line (vector) the interrupt is connected to.
Page 873 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.1.14 ME_UMA—Management Engine UMA Register (MEI—D22:F0) Address Offset: 44h–47h Attribute: Default Value: 80000000h Size: 32 bits Description Reserved — RO. Hardwired to 1. Can be used by host software to discover that this register is valid.
Page 874 Description PME_Support (PSUP) — RO. This five-bit field indicates the power states in which the 15:11 function may assert PME#. Intel MEI can assert PME# from any D-state except D1 or D2 which are not supported by Intel MEI. 10:9 Reserved Aux_Current (AC) —...
Page 875 11 = D3 state The D1 and D2 states are not supported for the Intel MEI host controller. When in the state, the Intel ME’s configuration space is available, but the register memory spaces are not. Additionally, interrupts are blocked.
Page 876 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.1.21 MC—Message Signaled Interrupt Message Control Register (MEI—D22:F0) Address Offset: 8Eh–8Fh Attribute: R/W, RO Default Value: 0080h Size: 16 bits Description 15:8 Reserved. 64 Bit Address Capable (C64) — RO. Specifies that function is capable of generating 64-bit messages.
Page 877 Reserved. MEI Interrupt Delivery Mode (HIDM) — R/W. These bits control what type of interrupt the Intel MEI will send when ARC writes to set the M_IG bit in AUX space. They are interpreted as follows: 00 = Generate Legacy or MSI interrupt...
Page 878 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.1.27 HERX—MEI Extend Register DWX (MEI—D22:F0) Address Offset: HER1: C0h–C3h Attribute: HER2: C4h–C7h HER3: C8h–CBh HER4: CCh–CFh HER5: D0h–D3h HER6: D4h–D7h HER7: D8h–DBh HER8: DCh–DFh Default Value: 00000000h Size: 32 bits Description Extend Register DWX (ERDWX).
Page 879: Mei1 Configuration Registers Address Map
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.2 Second Management Engine Interface(MEI1) Configuration Registers (MEI—D22:F1) Table 23-1. MEI1 Configuration Registers Address Map (MEI —D22:F1) Offset Mnemonic Register Name Default Type 00h–01h Vendor Identification 8086h See register 02h–03h Device Identification description 04h–05h...
Page 880 Intel MEI is blocked from generating MSI to the host processor. NOTE: This bit does not block Intel MEI accesses to ME-UMA; that is, writes or reads to the host and ME circular buffers through the read window and write window registers still cause ME backbone transactions to ME-UMA.
Page 881 24 bits Description 23:16 Base Class Code (BCC) — RO. Indicates the base class code of the Intel MEI device. 15:8 Sub Class Code (SCC) — RO. Indicates the sub class code of the Intel MEI device. Programming Interface (PI) — RO. Indicates the programming interface of the Intel MEI device.
Page 882 – Default Value: 0000000000000004h Size: 64 bits This register allocates space for the Intel MEI memory mapped registers. Description Base Address (BA) — R/W. Software programs this field with the base address of 63:4 this region. Prefetchable Memory (PM) — RO. Indicates that this range is not pre-fetchable.
Page 883 0100h Size: 16 bits Description Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin the Intel MEI host 15:8 controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively. Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line (vector) the interrupt is connected to.
Page 884 Description PME_Support (PSUP) — RO. This five-bit field indicates the power states in which the 15:11 function may assert PME#. Intel MEI can assert PME# from any D-state except D1 or D2 which are not supported by Intel MEI. 10:9 Reserved Aux_Current (AC) —...
Page 885 11 = D3 state The D1 and D2 states are not supported for the Intel MEI host controller. When in the state, the Intel ME’s configuration space is available, but the register memory spaces are not. Additionally, interrupts are blocked.
Page 886 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.2.20 MC—Message Signaled Interrupt Message Control Register (MEI—D22:F1) Address Offset: 8Eh–8Fh Attribute: R/W, RO Default Value: 0080h Size: 16 bits Description 15:8 Reserved. 64 Bit Address Capable (C64) — RO. Specifies that function is capable of generating 64-bit messages.
Page 887 Reserved. Intel MEI Interrupt Delivery Mode (HIDM) — R/W. These bits control what type of interrupt the Intel MEI will send when ARC writes to set the M_IG bit in AUX space. They are interpreted as follows: 00 = Generate Legacy or MSI interrupt...
Page 888: Mei Mmio Register Address Map (Ve - D23:F0)
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.2.26 HERX—MEI Extend Register DWX (MEI—D22:F1) Address Offset: HER1: C0h–C3h Attribute: HER2: C4h–C7h HER3: C8h–CBh HER4: CCh–CFh HER5: D0h–D3h HER6: D4h–D7h HER7: D8h–DBh HER8: DCh–DFh Default Value: 00000000h Size: 32 bits Description Extend Register DWX (ERDWX): Xth DWORD result of the extend operation.
Page 889 Reserved Must be programmed to zero Host Reset (H_RST). Setting this bit to 1 will initiate a Intel MEI reset sequence to get the circular buffers into a known good state for host and ME communication. When this bit transitions from 0 to 1, hardware will clear the H_RDY and ME_RDY bits.
Page 890 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.3.4 ME CSR_HA—ME Control Status Host Access (MEI MMIO Register) Address Offset: MEI0_MBAR + 0Ch Attribute: Default Value: 02000000h Size: 32 bits Description ME Circular Buffer Depth Host Read Access (ME_CBD_HRA). 31:24 Host read only access to ME_CBD.
Page 891: Mei Mmio Register Address Map (Ve - D23:F0)
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.4 MEI1_MBAR—MEI0 MMIO Registers These MMIO registers are accessible starting at the MEI1 MMIO Base Address (MEI1_MBAR) which gets programmed into D22:F1:Offset 10–17h. These registers are reset by PLTRST# unless otherwise noted.
Page 892 Reserved Must be programmed to zero Host Reset (H_RST). Setting this bit to 1 will initiate a Intel MEI reset sequence to get the circular buffers into a known good state for host and ME communication. When this bit transitions from 0 to 1, hardware will clear the H_RDY and ME_RDY bits.
Page 893 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.4.4 ME CSR_HA—ME Control Status Host Access (MEI MMIO Register) Address Offset: MEI1_MBAR + 0Ch Attribute: Default Value: 02000000h Size: 32 bits Description ME Circular Buffer Depth Host Read Access (ME_CBD_HRA). 31:24 Host read only access to ME_CBD.
Page 894: Ide Function For Remote Boot And Installations Pt Ider Register Address Map
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.5 IDE Function for Remote Boot and Installations PT IDER Registers (IDER — D22:F2) Table 23-4. IDE Function for remote boot and Installations PT IDER Register Address Map Address Register Default Register Name...
Page 895 Address Offset: 00–01h Attribute: Default Value: 8086h Size: 16 bits Description 15:0 Vendor ID (VID) — RO. This is a 16-bit value assigned by Intel. 23.5.2 DID—Device Identification Register (IDER—D22:F2) Address Offset: 02–03h Attribute: Default Value: See bit description Size:...
Page 896 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.5.4 PCISTS—PCI Device Status Register (IDER—D22:F2) Address Offset: 06–07h Attribute: Default Value: 00B0h Size: 16 bits Description 15:11 Reserved DEVSEL# Timing Status (DEVT)—RO. This bit controls the device select time for 10:9 the PT function's PCI interface.
Page 897 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.5.8 PCMDBA—Primary Command Block IO Bar Register (IDER—D22:F2) Address Offset: 10–13h Attribute: RO, R/W Default Value: 00000001h Size: 32 bits Description 31:16 Reserved Base Address (BAR)—R/W Base Address of the BAR0 I/O space (8 consecutive I/O 15:3 locations).
Page 898 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.5.11 SCTLBA—Secondary Control Block base Address Register (IDER—D22:F2) Address Offset: 1C–1Fh Attribute: RO, R/W Default Value: 00000001h1 Size: 32 bits Description 31:16 Reserved Base Address (BAR)—R/W. Base Address of the I/O space (4 consecutive I/O 15:2 locations).
Page 899 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.5.15 CAPP—Capabilities List Pointer Register (IDER—D22:F2) Address Offset: 34h Attribute: Default Value: Size: 8 bits Description Capability Pointer (CP)— R/WO. This field indicates that the first capability pointer is offset C8h (the power management capability).
Page 900 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.5.18 PC—PCI Power Management Capabilities Register (IDER—D22:F2) Address Offset: CA–CBh Attribute: Default Value: 0023h Size: 16 bits Description PME_Support (PSUP) — RO. This five-bit field indicates the power states in which 15:11 the function may assert PME#.
Page 901 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.5.19 PMCS—PCI Power Management Control and Status Register (IDER—D22:F2) Address Offset: CC-CFh Attribute: RO, R/W Default Value: 00000000h Size: 32 bits Description 31:4 Reserved No Soft Reset (NSR) — RO. When set to 1, this bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset.
Page 902 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.5.21 MC—Message Signaled Interrupt Message Control Register (IDER—D22:F2) Address Offset: D2–D3h Attribute: RO, R/W Default Value: 0080h Size: 16 bits Description 15:8 Reserved 64 Bit Address Capable (C64) — RO. Capable of generating 64-bit and 32-bit messages.
Page 903 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6 IDE BAR0 Table 23-5. IDE BAR0 Register Address Map Address Register Default Register Name Attribute Offset Symbol Value IDEDATA IDE Data Register IDEERD1 IDE Error Register DEV1 IDEERD0 IDE Error Register DEV0...
Page 904 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.1 IDEDATA—IDE Data Register (IDER—D22:F2) Address Offset: 0h Attribute: Default Value: Size: 8 bits The IDE data interface is a special interface that is implemented in the HW. This data interface is mapped to IO space from the host and takes read and write cycles from the host targeting master or slave device.
Page 905 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.4 IDEFR—IDE Features Register (IDER—D22:F2) Address Offset: 01h Attribute: Default Value: Size: 8 bits This register implements the Feature register of the command block of the IDE function. This register can be written only by the Host.
Page 906 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.7 IDESCOR0—IDE Sector Count Out Register Device 0 Register (IDER—D22:F2) Address Offset: 02h Attribute: Default Value: Size: 8 bits This register is read by the HOST interface if DEV = 0. ME-Firmware writes to this register at the end of a command of the selected device.
Page 907 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.9 IDESNOR1—IDE Sector Number Out Register Device 1 Register (IDER—D22:F2) Address Offset: 03h Attribute: Default Value: Size: 8 bits This register is read by the Host if DEV = 1. ME-Firmware writes to this register at the end of a command of the selected device.
Page 908 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.11 IDECLIR—IDE Cylinder Low In Register Register (IDER—D22:F2) Address Offset: 04h Attribute: Default Value: Size: 8 bits This register implements the Cylinder Low register of the command block of the IDE function. This register can be written only by the Host. When host writes to this register, all 3 registers (IDECLIR, IDECLOR0, IDECLOR1) are updated with the written value.
Page 909 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.13 IDCLOR0—IDE Cylinder Low Out Register Device 0 Register (IDER—D22:F2) Address Offset: 04h Attribute: Default Value: Size: 8 bits This register is read by the Host if DEV = 0. ME-Firmware writes to this register at the end of a command of the selected device.
Page 910 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.15 IDCHOR1—IDE Cylinder High Out Register Device 1 Register (IDER—D22:F2) Address Offset: 05h Attribute: Default Value: Size: 8 bits This register is read by the Host if Device = 1. ME-Firmware writes to this register at the end of a command of the selected device.
Page 911 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.17 IDEDHIR—IDE Drive/Head In Register (IDER—D22:F2) Address Offset: 06h Attribute: Default Value: Size: 8 bits This register implements the Drive/Head register of the command block of the IDE. This register can be written only by the Host. When host writes to this register, all 3 registers (IDEDHIR, IDEDHOR0, IDEDHOR1) are updated with the written value.
Page 912 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.19 IDDHOR0—IDE Drive Head Out Register Device 0 Register (IDER—D22:F2) Address Offset: 06h Attribute: Default Value: Size: 8 bits This register is read only by the Host. Host read to this Drive/head In register address reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=0.
Page 913 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.6.21 IDESD1R—IDE Status Device 1 Register (IDER—D22:F2) Address Offset: 07h Attribute: Default Value: Size: 8 bits This register implements the status register of the slave device (DEV = 1). This register is read only by the Host. Host read of this register clears the slave device's interrupt.
Page 914 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.7 IDE BAR1 Address Register Default Register Name Attribute Offset Symbol Value IDDCR IDE Device Control Register RO, WO IDASR IDE Alternate status Register 23.7.1 IDDCR—IDE Device Control Register (IDER—D22:F2) Address Offset: 2h...
Page 915 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.8 IDE BAR4 Table 23-6. IDE BAR4 Register Address Map Address Register Default Register Name Attribute Offset Symbol Value IDE Primary Bus Master Command IDEPBMCR RO, R/W Register IDE Primary Bus Master Device Specific 0...
Page 916 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.8.1 IDEPBMCR—IDE Primary Bus Master Command Register (IDER—D22:F2) Address Offset: 00h Attribute: RO, R/W Default Value: Size: 8 bits This register implements the bus master command register of the primary channel. This register is programmed by the Host.
Page 917 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.8.3 IDEPBMSR—IDE Primary Bus Master Status Register (IDER—D22:F2) Address Offset: 02h Attribute: RO, R/W Default Value: Size: 8 bits Description Simplex Only (SO) — RO. Value indicates whether both Bus Master Channels can be operated at the same time or not.
Page 918 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.8.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor Table Pointer Byte 1 Register (IDER—D22:F2) Address Offset: 05h Attribute: Default Value: Size: 8 bits Description Descriptor Table Pointer Byte 1 (DTPB1) — R/W. This register implements the Byte 1 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the primary channel.
Page 919 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.8.9 IDESBMCR—IDE Secondary Bus Master Command Register (IDER—D22:F2) Address Offset: 08h Attribute: Default Value: Size: 8 bits Description Reserved Read Write Command (RWC) — R/W. This bit sets the direction of bus master transfer.
Page 920 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.8.12 IDESBMDS1R—IDE Secondary Bus Master Device Specific 1 Register (IDER—D22:F2) Address Offset: 0Bh Attribute: Default Value: Size: 8 bits Description Device Specific Data1 (DSD1) — R/W. This register implements the bus master Device Specific 1 register of the secondary channel.
Page 921 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.8.15 IDESBMDTPR2—IDE Secondary Bus Master Descriptor Table Pointer Byte 2 Register (IDER—D22:F2) Address Offset: 0Eh Attribute: Default Value: Size: 8 bits Description Descriptor Table Pointer Byte 2 (DTPB2) — R/W. This register implements the Byte 2 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the secondary channel.
Page 922 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.9 Serial Port for Remote Keyboard and Text (KT) Redirection (KT — D22:F3) Table 23-7. Serial Port for Remote Keyboard and Text (KT) Redirection Register Address Map Address Register Default Register Name...
Page 923 Address Offset: 00–01h Attribute: Default Value: 8086h Size: 16 bits Description 15:0 Vendor ID (VID) — RO. This is a 16-bit value assigned by Intel. 23.9.2 DID—Device Identification Register (KT—D22:F3) Address Offset: 02–03h Attribute: Default Value: See bit description Size:...
Page 924 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.9.4 STS—Device Status Register (KT—D22:F3) Address Offset: 06–07h Attribute: Default Value: 00B0h Size: 16 bits Description 15:11 Reserved DEVSEL# Timing Status (DEVT)— RO. This field controls the device select time for 10:9 the PT function's PCI interface.
Page 925 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.9.7 CLS—Cache Line Size Register (KT—D22:F3) Address Offset: 0Ch Attribute: Default Value: Size: 8 bits This register defines the system cache line size in DWORD increments. Mandatory for master which use the Memory-Write and Invalidate command.
Page 926 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.9.10 SVID—Subsystem Vendor ID Register (KT—D22:F3) Address Offset: 2Ch Attribute: R/WO – Default Value: 0000h Size: 16 bits Description Subsystem Vendor ID (SSVID) — R/WO. Indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this 15:0 register becomes Read Only.
Page 927 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.9.14 PID—PCI Power Management Capability ID Register (KT—D22:F3) Address Offset: C8–C9h Attribute: Default Value: D001h Size: 16 bits Description 15:8 Next Capability (NEXT)— RO. A value of D0h points to the MSI capability.
Page 928 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.9.17 MC—Message Signaled Interrupt Message Control Register (KT—D22:F3) Address Offset: D2–D3h Attribute: RO, R/W Default Value: 0080h Size: 16 bits Description 15:8 Reserved 64 Bit Address Capable (C64)— RO. Capable of generating 64-bit and 32-bit messages.
Page 929 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.9.20 MD—Message Signaled Interrupt Message Data Register (KT—D22:F3) Address Offset: DC–DDh Attribute: Default Value: 0000h Size: 16 bits This 16-bit field is programmed by system software if MSI is enabled Description Data (DATA)— R/W. This MSI data is driven onto the lower word of the data bus of 15:0 the MSI memory write transaction.
Page 930 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.10.1 KTRxBR—KT Receive Buffer Register (KT—D23:F3) Address Offset: 00h Attribute: Default Value: Size: 8 bits This implements the KT Receiver Data register. Host access to this address, depends on the state of the DLAB bit (KTLCR[7]). It must be 0 to access the KTRxBR.
Page 931 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.10.4 KTIER—KT Interrupt Enable Register (KT—D23:F3) Address Offset: 01h Attribute: Default Value: Size: 8 bits This implements the KT Interrupt Enable register. Host access to this address, depends on the state of the DLAB bit (KTLCR[7]). It must be "0" to access this register. The bits enable specific events to interrupt the Host.
Page 932 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.10.6 KTIIR—KT Interrupt Identification Register (KT—D23:F3) Address Offset: 02h Attribute: Default Value: Size: 8 bits The KT IIR register prioritizes the interrupts from the function into 4 levels and records them in the IIR_STAT field of the register. When Host accesses the IIR, hardware freezes all interrupts and provides the priority to the Host.
Page 933 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.10.8 KTLCR—KT Line Control Register (KT—D23:F3) Address Offset: 03h Attribute: Default Value: Size: 8 bits The line control register specifies the format of the asynchronous data communications exchange and sets the DLAB bit. Most bits in this register have no affect on hardware and are only used by the FW.
Page 934 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.10.10 KTLSR—KT Line Status Register (KT—D23:F3) Address Offset: 05h Attribute: Default Value: Size: 8 bits This register provides status information of the data transfer to the Host. Error indication, etc. are provided by the HW/FW to the host using this register.
Page 935 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) 23.10.11 KTMSR—KT Modem Status Register (KT—D23:F3) Address Offset: 06h Attribute: Default Value: Size: 8 bits The functionality of the Modem is emulated by the FW. This register provides the status of the current state of the control lines from the modem.
Page 936 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0) Datasheet...

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